Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.

llvm-svn: 48380

5 files changed, 0 insertions, 40 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
index b4b67a2d207..6977093923a 100644
--- a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -59,12 +59,6 @@ FunctionPass *llvm::createPPCBranchSelectionPass() {
 ///
 static unsigned getNumBytesForInstruction(MachineInstr *MI) {
   switch (MI->getOpcode()) {
-  case PPC::IMPLICIT_DEF_GPRC: // no asm emitted
-  case PPC::IMPLICIT_DEF_G8RC: // no asm emitted
-  case PPC::IMPLICIT_DEF_F4:   // no asm emitted
-  case PPC::IMPLICIT_DEF_F8:   // no asm emitted
-  case PPC::IMPLICIT_DEF_VRRC: // no asm emitted
-    return 0;
   case PPC::INLINEASM: {       // Inline Asm: Variable size.
     MachineFunction *MF = MI->getParent()->getParent();
     const char *AsmStr = MI->getOperand(0).getSymbolName();
diff --git a/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
index a23f4e41eb6..d2bbebbed97 100644
--- a/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -112,12 +112,6 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
     case TargetInstrInfo::LABEL:
       MCE.emitLabel(MI.getOperand(0).getImm());
       break;
-    case PPC::IMPLICIT_DEF_GPRC:
-    case PPC::IMPLICIT_DEF_G8RC:
-    case PPC::IMPLICIT_DEF_F8:
-    case PPC::IMPLICIT_DEF_F4:
-    case PPC::IMPLICIT_DEF_VRRC:
-      break; // pseudo opcode, no side effects
     case PPC::MovePCtoLR:
     case PPC::MovePCtoLR8:
       assert(TM.getRelocationModel() == Reloc::PIC_);
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index e7b734f76b6..0b7d1cc42a7 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -54,14 +54,6 @@ def HI48_64 : SDNodeXForm<imm, [{
 
 
 //===----------------------------------------------------------------------===//
-// Pseudo instructions.
-//
-
-def IMPLICIT_DEF_G8RC : Pseudo<(outs G8RC:$rD), (ins),"; IMPLICIT_DEF_G8RC $rD",
-                              [(set G8RC:$rD, (undef))]>;
-
-
-//===----------------------------------------------------------------------===//
 // Calls.
 //
 
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
index c006ce0becb..feb538a6fa3 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -160,9 +160,6 @@ class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
 //===----------------------------------------------------------------------===//
 // Instruction Definitions.
 
-def IMPLICIT_DEF_VRRC : Pseudo<(outs VRRC:$rD), (ins),"; IMPLICIT_DEF_VRRC $rD",
-                               [(set VRRC:$rD, (v4i32 (undef)))]>;
-
 def DSS      : DSS_Form<822, (outs),
                         (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
                         "dss $STRM", LdStGeneral /*FIXME*/, []>;
@@ -579,11 +576,6 @@ def : Pat<(int_ppc_altivec_dstst G8RC:$rA, GPRC:$rB, imm:$STRM),
 def : Pat<(int_ppc_altivec_dststt G8RC:$rA, GPRC:$rB, imm:$STRM),
           (DSTSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
 
-// Undef.
-def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VRRC)>;
-def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VRRC)>;
-def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VRRC)>;
-
 // Loads.
 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
 
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index ed910a9722c..f51158d3b1a 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -335,18 +335,6 @@ def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
                        [(set GPRC:$result,
                              (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
                          
-let isImplicitDef = 1 in {
-def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins),
-                              "${:comment}IMPLICIT_DEF_GPRC $rD",
-                              [(set GPRC:$rD, (undef))]>;
-def IMPLICIT_DEF_F8  : Pseudo<(outs F8RC:$rD), (ins),
-                              "${:comment} IMPLICIT_DEF_F8 $rD",
-                              [(set F8RC:$rD, (undef))]>;
-def IMPLICIT_DEF_F4  : Pseudo<(outs F4RC:$rD), (ins),
-                              "${:comment} IMPLICIT_DEF_F4 $rD",
-                              [(set F4RC:$rD, (undef))]>;
-}
-
 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded by the
 // scheduler into a branch sequence.
 let usesCustomDAGSchedInserter = 1,    // Expanded by the scheduler.