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path: root/llvm/lib/Target/PowerPC/README_ALTIVEC.txt
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* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-1/+1
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* [PowerPC] Flow oversized lines for r235309Bill Schmidt2015-04-201-11/+25
| | | | llvm-svn: 235310
* [PowerPC] Add future work for vector insert/extract to README_ALTIVEC.txtBill Schmidt2015-04-201-0/+14
| | | | llvm-svn: 235309
* Correct 'teh' and other typos / repeated words.Ed Maste2015-04-141-1/+1
| | | | | | | | Patch by Eitan Adler. Differential Revision: http://reviews.llvm.org/D8514 llvm-svn: 234939
* Updated with list of possible improvements we are tracking internallyKit Barton2015-03-111-0/+33
| | | | llvm-svn: 231946
* Add LLVM support for PPC cryptography builtinsNemanja Ivanovic2015-03-041-0/+45
| | | | | | Review: http://reviews.llvm.org/D7955 llvm-svn: 231285
* Add the following 64-bit vector integer arithmetic instructions added in POWER8:Kit Barton2015-03-031-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | vaddudm vsubudm vmulesw vmulosw vmuleuw vmulouw vmuluwm vmaxsd vmaxud vminsd vminud vcmpequd vcmpequd. vcmpgtsd vcmpgtsd. vcmpgtud vcmpgtud. vrld vsld vsrd vsrad Phabricator review: http://reviews.llvm.org/D7959 llvm-svn: 231115
* add a noteChris Lattner2008-04-251-0/+23
| | | | llvm-svn: 50267
* readme updatesNate Begeman2008-02-131-0/+9
| | | | llvm-svn: 47051
* Add a noteChris Lattner2006-04-281-0/+8
| | | | llvm-svn: 27999
* add a noteChris Lattner2006-04-191-0/+31
| | | | llvm-svn: 27832
* add a noteChris Lattner2006-04-191-0/+30
| | | | llvm-svn: 27828
* add a noteChris Lattner2006-04-181-0/+23
| | | | llvm-svn: 27809
* Implement an important entry from README_ALTIVEC:Chris Lattner2006-04-181-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an altivec predicate compare is used immediately by a branch, don't use a (serializing) MFCR instruction to read the CR6 register, which requires a compare to get it back to CR's. Instead, just branch on CR6 directly. :) For example, for: void foo2(vector float *A, vector float *B) { if (!vec_any_eq(*A, *B)) *B = (vector float){0,0,0,0}; } We now generate: _foo2: mfspr r2, 256 oris r5, r2, 12288 mtspr 256, r5 lvx v2, 0, r4 lvx v3, 0, r3 vcmpeqfp. v2, v3, v2 bne cr6, LBB1_2 ; UnifiedReturnBlock LBB1_1: ; cond_true vxor v2, v2, v2 stvx v2, 0, r4 mtspr 256, r2 blr LBB1_2: ; UnifiedReturnBlock mtspr 256, r2 blr instead of: _foo2: mfspr r2, 256 oris r5, r2, 12288 mtspr 256, r5 lvx v2, 0, r4 lvx v3, 0, r3 vcmpeqfp. v2, v3, v2 mfcr r3, 2 rlwinm r3, r3, 27, 31, 31 cmpwi cr0, r3, 0 beq cr0, LBB1_2 ; UnifiedReturnBlock LBB1_1: ; cond_true vxor v2, v2, v2 stvx v2, 0, r4 mtspr 256, r2 blr LBB1_2: ; UnifiedReturnBlock mtspr 256, r2 blr This implements CodeGen/PowerPC/vec_br_cmp.ll. llvm-svn: 27804
* move some stuff around, clean things upChris Lattner2006-04-181-14/+11
| | | | llvm-svn: 27802
* Implement v16i8 multiply with this code:Chris Lattner2006-04-181-9/+0
| | | | | | | | | | | | | | | | vmuloub v5, v3, v2 vmuleub v2, v3, v2 vperm v2, v2, v5, v4 This implements CodeGen/PowerPC/vec_mul.ll. With this, v16i8 multiplies are 6.79x faster than before. Overall, UnitTests/Vector/multiplies.c is now 2.45x faster with LLVM than with GCC. Remove the 'integer multiplies' todo from the README file. llvm-svn: 27792
* remove done itemChris Lattner2006-04-171-19/+2
| | | | llvm-svn: 27778
* add a noteChris Lattner2006-04-171-0/+10
| | | | llvm-svn: 27758
* Implement a TODO: for any shuffle that can be viewed as a v4[if]32 shuffle,Chris Lattner2006-04-171-12/+0
| | | | | | | if it can be implemented in 3 or fewer discrete altivec instructions, codegen it as such. This implements Regression/CodeGen/PowerPC/vec_perf_shuffle.ll llvm-svn: 27748
* Implement a TODO: have the legalizer canonicalize a bunch of operations toChris Lattner2006-04-161-18/+2
| | | | | | | one type (v4i32) so that we don't have to write patterns for each type, and so that more CSE opportunities are exposed. llvm-svn: 27731
* Make the BUILD_VECTOR lowering code much more aggressive w.r.t constant vectors.Chris Lattner2006-04-161-20/+10
| | | | | | Remove some done items from the todo list. llvm-svn: 27729
* add a note, move an altivec todo to the altivec list.Chris Lattner2006-04-131-0/+10
| | | | llvm-svn: 27654
* Add a new way to match vector constants, which make it easier to bang bits ofChris Lattner2006-04-121-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | different types. Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load, implementing PowerPC/vec_constants.ll:test1. This compiles: typedef float vf __attribute__ ((vector_size (16))); typedef int vi __attribute__ ((vector_size (16))); void test(vi *P1, vi *P2, vf *P3) { *P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000}; *P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF}; *P3 = vec_abs((vector float)*P3); } to: _test: mfspr r2, 256 oris r6, r2, 49152 mtspr 256, r6 vspltisw v0, -1 vslw v0, v0, v0 lvx v1, 0, r3 vand v1, v1, v0 stvx v1, 0, r3 lvx v1, 0, r4 vandc v1, v1, v0 stvx v1, 0, r4 lvx v1, 0, r5 vandc v0, v1, v0 stvx v0, 0, r5 mtspr 256, r2 blr instead of (with two constant pool entries): _test: mfspr r2, 256 oris r6, r2, 49152 mtspr 256, r6 li r6, lo16(LCPI1_0) lis r7, ha16(LCPI1_0) li r8, lo16(LCPI1_1) lis r9, ha16(LCPI1_1) lvx v0, r7, r6 lvx v1, 0, r3 vand v0, v1, v0 stvx v0, 0, r3 lvx v0, r9, r8 lvx v1, 0, r4 vand v1, v1, v0 stvx v1, 0, r4 lvx v1, 0, r5 vand v0, v1, v0 stvx v0, 0, r5 mtspr 256, r2 blr GCC produces (with 2 cp entries): _test: mfspr r0,256 stw r0,-4(r1) oris r0,r0,0xc00c mtspr 256,r0 lis r2,ha16(LC0) lis r9,ha16(LC1) la r2,lo16(LC0)(r2) lvx v0,0,r3 lvx v1,0,r5 la r9,lo16(LC1)(r9) lwz r12,-4(r1) lvx v12,0,r2 lvx v13,0,r9 vand v0,v0,v12 stvx v0,0,r3 vspltisw v0,-1 vslw v12,v0,v0 vandc v1,v1,v12 stvx v1,0,r5 lvx v0,0,r4 vand v0,v0,v13 stvx v0,0,r4 mtspr 256,r12 blr llvm-svn: 27624
* we have a shuffle instr, add an example.Chris Lattner2006-04-111-5/+6
| | | | llvm-svn: 27592
* Add an itemChris Lattner2006-04-061-1/+6
| | | | llvm-svn: 27470
* Pattern match vmrg* instructions, which are now lowered by the CFE into ↵Chris Lattner2006-04-061-3/+0
| | | | | | shuffles. llvm-svn: 27457
* remove two done itemsChris Lattner2006-04-061-10/+0
| | | | llvm-svn: 27453
* Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. toChris Lattner2006-04-061-5/+0
| | | | | | | lower it and LLVM to have one fewer intrinsic. This implements CodeGen/PowerPC/vec_shuffle.ll llvm-svn: 27450
* Add all of the data stream intrinsics and instructions. wooChris Lattner2006-04-051-7/+0
| | | | llvm-svn: 27442
* add vmladduhmChris Lattner2006-04-051-2/+0
| | | | llvm-svn: 27423
* add a noteChris Lattner2006-04-041-2/+4
| | | | llvm-svn: 27419
* add a noteChris Lattner2006-04-041-2/+13
| | | | llvm-svn: 27414
* Remove done itemChris Lattner2006-04-021-5/+0
| | | | llvm-svn: 27351
* add a noteChris Lattner2006-04-021-0/+11
| | | | llvm-svn: 27348
* add a noteChris Lattner2006-03-311-0/+2
| | | | llvm-svn: 27302
* Implement an item from the readme, folding vcmp/vcmp. instructions withChris Lattner2006-03-311-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | identical instructions into a single instruction. For example, for: void test(vector float *x, vector float *y, int *P) { int v = vec_any_out(*x, *y); *x = (vector float)vec_cmpb(*x, *y); *P = v; } we now generate: _test: mfspr r2, 256 oris r6, r2, 49152 mtspr 256, r6 lvx v0, 0, r4 lvx v1, 0, r3 vcmpbfp. v0, v1, v0 mfcr r4, 2 stvx v0, 0, r3 rlwinm r3, r4, 27, 31, 31 xori r3, r3, 1 stw r3, 0(r5) mtspr 256, r2 blr instead of: _test: mfspr r2, 256 oris r6, r2, 57344 mtspr 256, r6 lvx v0, 0, r4 lvx v1, 0, r3 vcmpbfp. v2, v1, v0 mfcr r4, 2 *** vcmpbfp v0, v1, v0 rlwinm r4, r4, 27, 31, 31 stvx v0, 0, r3 xori r3, r4, 1 stw r3, 0(r5) mtspr 256, r2 blr Testcase here: CodeGen/PowerPC/vcmp-fold.ll llvm-svn: 27290
* These are doneChris Lattner2006-03-311-5/+0
| | | | llvm-svn: 27284
* add a noteChris Lattner2006-03-291-0/+4
| | | | llvm-svn: 27243
* add a noteChris Lattner2006-03-281-0/+10
| | | | llvm-svn: 27227
* Add a few more altivec intrinsicsNate Begeman2006-03-281-2/+0
| | | | llvm-svn: 27215
* implement a bunch more intrinsics.Chris Lattner2006-03-281-10/+1
| | | | llvm-svn: 27209
* Add a bunch of notes from my journey thus far.Chris Lattner2006-03-271-9/+103
| | | | llvm-svn: 27170
* Split out altivec notes into their own READMEChris Lattner2006-03-271-0/+54
llvm-svn: 27168
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