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path: root/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
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* Add VSX Scalar loads and stores to the PPC back endNemanja Ivanovic2015-05-071-0/+3
* This patch adds ABI support for v1i128 data type.Kit Barton2015-05-051-1/+1
* Add Hardware Transactional Memory (HTM) SupportKit Barton2015-03-251-0/+2
* [PowerPC] Add support for the QPX vector instruction setHal Finkel2015-02-251-0/+23
* Get the cached subtarget off the MachineFunction rather thanEric Christopher2015-02-201-4/+4
* [PowerPC] Implement the vpopcnt instructions for POWER8Bill Schmidt2015-02-031-1/+1
* [PowerPC] Make r2 allocatable on PPC64/ELF for some leaf functionsHal Finkel2015-02-011-4/+37
* [PowerPC] Add DWARF numbers for CA (XER), etc.Hal Finkel2015-01-131-5/+4
* [PowerPC] Don't use a non-allocatable register to implement the 'cc' aliasHal Finkel2014-12-081-9/+0
* [PowerPC] 'cc' should be an alias only to 'cr0'Hal Finkel2014-12-041-4/+2
* [PowerPC] Add a full condition code register to make the "cc" clobber workHal Finkel2014-04-041-0/+12
* [PowerPC] Add subregister classes for f64 VSX valuesHal Finkel2014-03-291-6/+30
* [PowerPC] Add v2i64 as a legal VSX typeHal Finkel2014-03-261-3/+3
* [PowerPC] Initial support for the VSX instruction setHal Finkel2014-03-131-0/+43
* Add CR-bit tracking to the PowerPC backend for i1 valuesHal Finkel2014-02-281-7/+6
* PPC: Add base-pointer support to builtin setjmp/longjmpHal Finkel2013-07-171-2/+6
* Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handlingHal Finkel2013-07-021-1/+1
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-5/+5
* Print PPC ZERO as 0 (not r0) even on DarwinHal Finkel2013-03-271-2/+2
* Remove the link register from the GPR classes on PowerPC.Bill Schmidt2013-03-271-2/+2
* Restore real bit lengths on PPC register numbersHal Finkel2013-03-261-12/+12
* PPC: Use HWEncoding and TRI->getEncodingValueHal Finkel2013-03-261-13/+13
* Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register classHal Finkel2013-03-211-2/+3
* Correct PPC FRAMEADDR lowering using a pseudo-registerHal Finkel2013-03-211-2/+6
* Prepare to make r0 an allocatable register on PPCHal Finkel2013-03-191-0/+9
* More cleanup of PPC register definitions.Hal Finkel2013-01-251-64/+8
* Start cleanup of PPC register definitions using foreach loops.Hal Finkel2013-01-241-65/+7
* Mark the PPC CTRRC and CTRRC8 register classes as non-allocatable.Hal Finkel2012-06-081-2/+10
* Remove the SubRegClasses field from RegisterClass descriptions.Jakob Stoklund Olesen2012-05-041-3/+1
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-3/+3
* Use set operations instead of plain lists to enumerate register classes.Jakob Stoklund Olesen2011-06-151-33/+26
* Remove custom allocation order boilerplate that is no longer needed.Jakob Stoklund Olesen2011-06-091-59/+3
* Split ppc dwarf regnums into ppc64 and ppc32 flavours.Rafael Espindola2011-05-301-140/+140
* Dwarf register 0 is r0, remove incorrect entries.Rafael Espindola2011-05-291-2/+2
* Remove DwarfRegNum from the individual bits of the condition register.Rafael Espindola2011-05-271-32/+32
* Fix some dwarf register numbers.Rafael Espindola2011-05-261-1/+1
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs a...Anton Korobeynikov2011-01-101-4/+4
* Restore the behavior of frame lowering before my refactoring.Anton Korobeynikov2010-12-181-4/+6
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-5/+6
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-19/+11
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-11/+19
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-19/+11
* Remove NumberHack entirely.Jakob Stoklund Olesen2010-05-251-4/+4
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-241-8/+12
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-241-1/+1
* Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices areJakob Stoklund Olesen2010-05-241-0/+7
* Really reserve R2 on PPC Darwin. PR 6314.Dale Johannesen2010-02-161-8/+4
* Model the carry bit on ppc32. Without this we couldDale Johannesen2009-09-181-0/+8
* Add support for the PowerPC 64-bit SVR4 ABI.Tilmann Scheller2009-08-151-3/+7
* Various small changes related to the Condition Register on PowerPC.Tilmann Scheller2009-07-031-14/+17
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