| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random nu... | Chuang-Yu Cheng | 2016-04-06 | 1 | -0/+20 |
| * | Add VSX Scalar loads and stores to the PPC back end | Nemanja Ivanovic | 2015-05-07 | 1 | -0/+3 |
| * | This patch adds ABI support for v1i128 data type. | Kit Barton | 2015-05-05 | 1 | -1/+1 |
| * | Add Hardware Transactional Memory (HTM) Support | Kit Barton | 2015-03-25 | 1 | -0/+2 |
| * | [PowerPC] Add support for the QPX vector instruction set | Hal Finkel | 2015-02-25 | 1 | -0/+23 |
| * | Get the cached subtarget off the MachineFunction rather than | Eric Christopher | 2015-02-20 | 1 | -4/+4 |
| * | [PowerPC] Implement the vpopcnt instructions for POWER8 | Bill Schmidt | 2015-02-03 | 1 | -1/+1 |
| * | [PowerPC] Make r2 allocatable on PPC64/ELF for some leaf functions | Hal Finkel | 2015-02-01 | 1 | -4/+37 |
| * | [PowerPC] Add DWARF numbers for CA (XER), etc. | Hal Finkel | 2015-01-13 | 1 | -5/+4 |
| * | [PowerPC] Don't use a non-allocatable register to implement the 'cc' alias | Hal Finkel | 2014-12-08 | 1 | -9/+0 |
| * | [PowerPC] 'cc' should be an alias only to 'cr0' | Hal Finkel | 2014-12-04 | 1 | -4/+2 |
| * | [PowerPC] Add a full condition code register to make the "cc" clobber work | Hal Finkel | 2014-04-04 | 1 | -0/+12 |
| * | [PowerPC] Add subregister classes for f64 VSX values | Hal Finkel | 2014-03-29 | 1 | -6/+30 |
| * | [PowerPC] Add v2i64 as a legal VSX type | Hal Finkel | 2014-03-26 | 1 | -3/+3 |
| * | [PowerPC] Initial support for the VSX instruction set | Hal Finkel | 2014-03-13 | 1 | -0/+43 |
| * | Add CR-bit tracking to the PowerPC backend for i1 values | Hal Finkel | 2014-02-28 | 1 | -7/+6 |
| * | PPC: Add base-pointer support to builtin setjmp/longjmp | Hal Finkel | 2013-07-17 | 1 | -2/+6 |
| * | Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling | Hal Finkel | 2013-07-02 | 1 | -1/+1 |
| * | Make SubRegIndex size mandatory, following r183020. | Ahmed Bougacha | 2013-05-31 | 1 | -5/+5 |
| * | Print PPC ZERO as 0 (not r0) even on Darwin | Hal Finkel | 2013-03-27 | 1 | -2/+2 |
| * | Remove the link register from the GPR classes on PowerPC. | Bill Schmidt | 2013-03-27 | 1 | -2/+2 |
| * | Restore real bit lengths on PPC register numbers | Hal Finkel | 2013-03-26 | 1 | -12/+12 |
| * | PPC: Use HWEncoding and TRI->getEncodingValue | Hal Finkel | 2013-03-26 | 1 | -13/+13 |
| * | Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register class | Hal Finkel | 2013-03-21 | 1 | -2/+3 |
| * | Correct PPC FRAMEADDR lowering using a pseudo-register | Hal Finkel | 2013-03-21 | 1 | -2/+6 |
| * | Prepare to make r0 an allocatable register on PPC | Hal Finkel | 2013-03-19 | 1 | -0/+9 |
| * | More cleanup of PPC register definitions. | Hal Finkel | 2013-01-25 | 1 | -64/+8 |
| * | Start cleanup of PPC register definitions using foreach loops. | Hal Finkel | 2013-01-24 | 1 | -65/+7 |
| * | Mark the PPC CTRRC and CTRRC8 register classes as non-allocatable. | Hal Finkel | 2012-06-08 | 1 | -2/+10 |
| * | Remove the SubRegClasses field from RegisterClass descriptions. | Jakob Stoklund Olesen | 2012-05-04 | 1 | -3/+1 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -3/+3 |
| * | Use set operations instead of plain lists to enumerate register classes. | Jakob Stoklund Olesen | 2011-06-15 | 1 | -33/+26 |
| * | Remove custom allocation order boilerplate that is no longer needed. | Jakob Stoklund Olesen | 2011-06-09 | 1 | -59/+3 |
| * | Split ppc dwarf regnums into ppc64 and ppc32 flavours. | Rafael Espindola | 2011-05-30 | 1 | -140/+140 |
| * | Dwarf register 0 is r0, remove incorrect entries. | Rafael Espindola | 2011-05-29 | 1 | -2/+2 |
| * | Remove DwarfRegNum from the individual bits of the condition register. | Rafael Espindola | 2011-05-27 | 1 | -32/+32 |
| * | Fix some dwarf register numbers. | Rafael Espindola | 2011-05-26 | 1 | -1/+1 |
| * | Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs a... | Anton Korobeynikov | 2011-01-10 | 1 | -4/+4 |
| * | Restore the behavior of frame lowering before my refactoring. | Anton Korobeynikov | 2010-12-18 | 1 | -4/+6 |
| * | Move hasFP() and few related hooks to TargetFrameInfo. | Anton Korobeynikov | 2010-11-18 | 1 | -5/+6 |
| * | Replace the SubRegSet tablegen class with a less error-prone mechanism. | Jakob Stoklund Olesen | 2010-05-26 | 1 | -19/+11 |
| * | Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." | Jakob Stoklund Olesen | 2010-05-26 | 1 | -11/+19 |
| * | Replace the SubRegSet tablegen class with a less error-prone mechanism. | Jakob Stoklund Olesen | 2010-05-26 | 1 | -19/+11 |
| * | Remove NumberHack entirely. | Jakob Stoklund Olesen | 2010-05-25 | 1 | -4/+4 |
| * | Switch SubRegSet to using symbolic SubRegIndices | Jakob Stoklund Olesen | 2010-05-24 | 1 | -8/+12 |
| * | Replace the tablegen RegisterClass field SubRegClassList with an alist-like data | Jakob Stoklund Olesen | 2010-05-24 | 1 | -1/+1 |
| * | Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are | Jakob Stoklund Olesen | 2010-05-24 | 1 | -0/+7 |
| * | Really reserve R2 on PPC Darwin. PR 6314. | Dale Johannesen | 2010-02-16 | 1 | -8/+4 |
| * | Model the carry bit on ppc32. Without this we could | Dale Johannesen | 2009-09-18 | 1 | -0/+8 |
| * | Add support for the PowerPC 64-bit SVR4 ABI. | Tilmann Scheller | 2009-08-15 | 1 | -3/+7 |
