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* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-1/+1
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Implement changes from Chris's feedback.Torok Edwin2009-07-081-2/+3
| | | | | | Finish converting lib/Target. llvm-svn: 75043
* Various small changes related to the Condition Register on PowerPC.Tilmann Scheller2009-07-031-2/+3
| | | | | | | | Don't spill to the CR save area when using the SVR4 ABI for now. Don't rely on constants assigned for registers to be in order (they aren't assigned in order). Make sure CR bits are mapped to the corresponding CR field. llvm-svn: 74767
* Refactor ABI code in the PowerPC backend.Tilmann Scheller2009-07-031-33/+31
| | | | | | | | | | | Make CalculateParameterAndLinkageAreaSize() Darwin-specific. Remove SVR4 specific code from LowerCALL_Darwin() and LowerFORMAL_ARGUMENTS_Darwin(). Rename MachoABI to DarwinABI for consistency. Rename ELF ABI to SVR4 ABI for consistency. Factor out common call return lowering between the Darwin and SVR4 ABI. Factor out common call lowering between the Darwin and SVR4 ABI. llvm-svn: 74766
* Implement the SVR4 ABI for PowerPC.Tilmann Scheller2009-07-031-18/+205
| | | | | | | | | | | | | | | | | | | | | | | | Implement LowerFORMAL_ARGUMENTS_SVR4(). Implement LowerCALL_SVR4(). Add support for split arguments. Implement by value parameter passing for aggregates. Add support for variable argument lists. Create the spill area for argument registers of variable argument functions no longer at a fixed offset. Make sure callee saved registers are spilled to the correct stack offsets. Change allocation order of non-volatile floating-point registers. Add VRSAVE to the list of callee-saved registers, add CallConvLowering for vararg calls. Add support for variable argument calls with Vector arguments. Add support for VR and VRSAVE save area, improve allocation order for non-volatile vector registers. Stop creating illegal i8 values in LowerVASTART(). Add memory access width hints. Make sure to reserve space on the stack for the frame pointer. When using the SVR4 ABI, reserve r13 for the Small Data Area pointer. Assure that the frame pointer is spilled to the correct location on the stack. Some FP registers were not marked as volatile. Make sure the i64 words from a long double are passed either both in registers or both on the stack. Only put integer arguments in registers which are not marked with the inreg flag. llvm-svn: 74765
* Add new function attribute - noredzone. Devang Patel2009-06-041-0/+1
| | | | | | | Update code generator to use this attribute and remove DisableRedZone target option. Update llc to set this attribute when -disable-red-zone command line option is used. llvm-svn: 72894
* Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling2009-05-131-20/+20
| | | | | | | | | | | | booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
* fix warning in -asserts build.Chris Lattner2009-03-261-4/+2
| | | | llvm-svn: 67736
* Fix a bunch of Doxygen syntax issues. Escape special characters,Dan Gohman2009-03-031-2/+2
| | | | | | and put @file directives on their own comment line. llvm-svn: 65920
* Remove refs to non-DebugLoc version of BuildMI from PowerPC.Dale Johannesen2009-02-131-80/+90
| | | | llvm-svn: 64431
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-0/+9
| | | | llvm-svn: 63938
* Respect the DisableRedZone flag on PowerPC.Dan Gohman2009-01-271-1/+2
| | | | llvm-svn: 63119
* Add a RM pseudoreg for the rounding mode, whichDale Johannesen2008-10-291-1/+2
| | | | | | | | | | | | | | | | | allows ppcf128->int conversion to work with DeadInstructionElimination. This is now turned off but RM is harmless. It does not do a complete job of modeling the rounding mode. Revert marking MFCR as using all 7 CR subregisters; while correct, this caused the problem in PR 2964, plus the local RA crash noted in the comments. This was needed to make DeadInstructionElimination, but as we are not running that, it is backed out for now. Eventually it should go back in and the other problems fixed where they're broken. llvm-svn: 58391
* Rewrite logic to figure out whether LR needs toDale Johannesen2008-10-241-23/+23
| | | | | | | | be saved/restored in the prolog/epilog. We need to do this iff something in the function stores into it. llvm-svn: 58116
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-4/+4
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Temporarily reverting r56683. This is causing a failure during the build of ↵Bill Wendling2008-09-261-1/+0
| | | | | | | | | | | | | | | | | llvm-gcc: /Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311. ../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://developer.apple.com/bugreporter> for instructions. {standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb" {standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression {standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb" ... llvm-svn: 56703
* Fix @llvm.frameaddress codegen. FP elimination optimization should be ↵Evan Cheng2008-09-261-0/+1
| | | | | | disabled when frame address is desired. Also add support for depth > 0. llvm-svn: 56683
* Remove isImm(), isReg(), and friends, in favor of Dan Gohman2008-09-131-2/+2
| | | | | | | | | isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. llvm-svn: 56189
* Trim unnecessary #includes.Dan Gohman2008-07-111-1/+0
| | | | llvm-svn: 53471
* Simplify this use of BuildMI. This is also in preparation forDan Gohman2008-07-071-3/+1
| | | | | | pool-allocating MachineInstrs. llvm-svn: 53198
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-2/+2
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
* Tail call optimization improvements:Arnold Schwaighofer2008-04-301-9/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move platform independent code (lowering of possibly overwritten arguments, check for tail call optimization eligibility) from target X86ISelectionLowering.cpp to TargetLowering.h and SelectionDAGISel.cpp. Initial PowerPC tail call implementation: Support ppc32 implemented and tested (passes my tests and test-suite llvm-test). Support ppc64 implemented and half tested (passes my tests). On ppc tail call optimization is performed if caller and callee are fastcc call is a tail call (in tail call position, call followed by ret) no variable argument lists or byval arguments option -tailcallopt is enabled Supported: * non pic tail calls on linux/darwin * module-local tail calls on linux(PIC/GOT)/darwin(PIC) * inter-module tail calls on darwin(PIC) If constraints are not met a normal call will be emitted. A test checking the argument lowering behaviour on x86-64 was added. llvm-svn: 50477
* Reverse sense of unwind-tables option. This meansDale Johannesen2008-04-141-1/+1
| | | | | | | stack tracebacks on Darwin x86-64 won't work by default; nevertheless, everybody but me thinks this is a good idea. llvm-svn: 49663
* Implement new llc flag -disable-required-unwind-tables.Dale Johannesen2008-04-081-1/+2
| | | | | | Corresponds to -fno-unwind-tables (usually default in gcc). llvm-svn: 49361
* Cosmetic changes per EH patch review feedback.Dale Johannesen2008-04-021-3/+3
| | | | llvm-svn: 49096
* Recommitting EH patch; this should answer most of theDale Johannesen2008-04-021-2/+5
| | | | | | | | | | | | | | | review feedback. -enable-eh is still accepted but doesn't do anything. EH intrinsics use Dwarf EH if the target supports that, and are handled by LowerInvoke otherwise. The separation of the EH table and frame move data is, I think, logically figured out, but either one still causes full EH info to be generated (not sure how to split the metadata correctly). MachineModuleInfo::needsFrameInfo is no longer used and is removed. llvm-svn: 49064
* Revert 49006 for the moment.Dale Johannesen2008-04-011-5/+2
| | | | llvm-svn: 49046
* Emit exception handling info for functions which areDale Johannesen2008-03-311-2/+5
| | | | | | | | | | | not marked nounwind, or for all functions when -enable-eh is set, provided the target supports Dwarf EH. llvm-gcc generates nounwind in the right places; other FEs will need to do so also. Given such a FE, -enable-eh should no longer be needed. llvm-svn: 49006
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-311-9/+0
| | | | llvm-svn: 48995
* detabify llvm, patch by Mike Stump!Chris Lattner2008-03-201-21/+21
| | | | llvm-svn: 48577
* Disable prolog code that aligns the stack when aDale Johannesen2008-03-101-7/+17
| | | | | | | | | | | | | | local object of >16 byte alignment exists. It does not work and getting it to work is not trivial, as explained in the comment. This fixes all the remaining ppc32 failures in the struct-layout-1 part of the gcc testsuite. (gcc does not support this either, and the only way to get such an object is with __attribute__((aligned)) or generic vectors; it can't be done in a standard-conforming program, or with Altivec. So I think disabling it is OK.) llvm-svn: 48188
* Change the "enable/disable" mechanism so that we can enable PPC registerBill Wendling2008-03-101-12/+19
| | | | | | scavenging for 32-bit and 64-bit separately. llvm-svn: 48186
* Add description of individual bits in CR. This fix PR1765.Nicolas Geoffray2008-03-101-32/+65
| | | | llvm-svn: 48143
* Removed spurious EnablePPCRS check.Bill Wendling2008-03-041-4/+3
| | | | llvm-svn: 47918
* Use a command-line option to turn register scavenging on/off for PPC.Bill Wendling2008-03-041-32/+43
| | | | llvm-svn: 47915
* This is the initial check-in for adding register scavenging to PPC. (Currently,Bill Wendling2008-03-031-68/+288
| | | | | | | | | PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that it uses a register other than the default R0 register (the scavenger scrounges for one). A significant part of this patch fixes how kill information is handled. llvm-svn: 47863
* Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR.Chris Lattner2008-02-131-0/+1
| | | | llvm-svn: 47067
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+2
| | | | llvm-svn: 46930
* Remove the nasty LABEL hack with a much less evil one. Now ↵Evan Cheng2008-02-011-10/+0
| | | | | | llvm.dbg.func.start implies a stoppoint is set. SelectionDAGISel records a new source line but does not create a ISD::LABEL node for this special stoppoint. Asm printer will magically print this label. This ensures nothing is emitted before. llvm-svn: 46635
* Add an extra operand to LABEL nodes which distinguishes between debug, EH, ↵Evan Cheng2008-01-311-4/+4
| | | | | | or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution. llvm-svn: 46609
* Makes the same change in ppc backend: avoid inserting prologue before debug ↵Evan Cheng2008-01-311-0/+10
| | | | | | labels. llvm-svn: 46596
* rename MachineInstr::setInstrDescriptor -> setDescChris Lattner2008-01-111-1/+1
| | | | llvm-svn: 45871
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-1/+1
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-2/+1
| | | | llvm-svn: 45680
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-79/+0
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-228/+0
| | | | llvm-svn: 45484
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-28/+0
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-9/+12
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-7/+6
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-4/+4
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
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