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path: root/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
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* rename MachineInstr::setInstrDescriptor -> setDescChris Lattner2008-01-111-1/+1
| | | | llvm-svn: 45871
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-1/+1
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-2/+1
| | | | llvm-svn: 45680
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-79/+0
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-228/+0
| | | | llvm-svn: 45484
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-28/+0
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-9/+12
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-7/+6
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-4/+4
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Fix a significant code quality regression I introduced on PPC64 quite Chris Lattner2007-12-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a while ago. We now produce: _foo: mflr r0 std r0, 16(r1) ld r2, 16(r1) std r2, 0(r3) ld r0, 16(r1) mtlr r0 blr instead of: _foo: mflr r0 std r0, 16(r1) lis r0, 0 ori r0, r0, 16 ldx r2, r1, r0 std r2, 0(r3) ld r0, 16(r1) mtlr r0 blr for: void foo(void **X) { *X = __builtin_return_address(0); } on ppc64. llvm-svn: 44701
* implement __builtin_return_addr(0) on ppc.Chris Lattner2007-12-081-2/+7
| | | | llvm-svn: 44700
* refactor some code to avoid overloading the name 'usesLR' in Chris Lattner2007-12-081-7/+9
| | | | | | | different places to mean different things. Document what the one in PPCFunctionInfo means and when it is valid. llvm-svn: 44699
* Fix a compilation warning.Evan Cheng2007-12-081-1/+1
| | | | llvm-svn: 44691
* Added canFoldMemoryOperand for PPC.Evan Cheng2007-12-051-0/+20
| | | | llvm-svn: 44623
* Add a argument to storeRegToStackSlot and storeRegToAddr to specify whetherEvan Cheng2007-12-051-13/+15
| | | | | | the stored register is killed. llvm-svn: 44600
* Remove redundant foldMemoryOperand variants and other code clean up.Evan Cheng2007-12-021-2/+5
| | | | llvm-svn: 44517
* Fix a crash on invalid code due to memcpy lowering.Chris Lattner2007-11-271-25/+30
| | | | llvm-svn: 44378
* Add parameter to getDwarfRegNum to permit targetsDale Johannesen2007-11-131-1/+1
| | | | | | | | to use different mappings for EH and debug info; no functional change yet. Fix warning in X86CodeEmitter. llvm-svn: 44056
* Completely forgot, that we have some debug information emission on PPC. This ↵Anton Korobeynikov2007-11-121-2/+2
| | | | | | | | should fix some regressions on ppc nightly tests. llvm-svn: 44029
* Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov2007-11-111-0/+5
| | | | | | | | This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, llvm-svn: 43997
* - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but ↵Evan Cheng2007-10-181-2/+2
| | | | | | | | only returns the opcode of the instruction post unfolding. - Fix some copy+paste bugs. llvm-svn: 43153
* Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister ↵Evan Cheng2007-10-181-6/+6
| | | | | | public interface. llvm-svn: 43150
* Fix a bug handling frame references in ppc inline asm when the frame offsetChris Lattner2007-10-161-24/+33
| | | | | | doesn't fit into 16 bits. llvm-svn: 43032
* - Added a few target hooks to generate load / store instructions from / to anyEvan Cheng2007-10-051-47/+154
| | | | | | | | address (not just from / to frameindexes). - Added target hooks to unfold load / store instructions / SDNodes into separate load, data processing, store instructions / SDNodes. llvm-svn: 42621
* Allow copyRegToReg to emit cross register classes copies.Evan Cheng2007-09-261-7/+13
| | | | | | Tested with "make check"! llvm-svn: 42346
* Fix comments.Evan Cheng2007-09-141-4/+4
| | | | llvm-svn: 41947
* Add missing index versions of instructions to the map.Bill Wendling2007-09-071-1/+7
| | | | llvm-svn: 41776
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-2/+2
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Long live the exception handling!Anton Korobeynikov2007-07-141-2/+3
| | | | | | | | | | | | | | | This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. llvm-svn: 39855
* eliminateFrameIndex() change.Evan Cheng2007-05-011-1/+3
| | | | llvm-svn: 36626
* Match MachineFunction::UsedPhysRegs changes.Evan Cheng2007-04-251-7/+6
| | | | llvm-svn: 36452
* The PPC64 ELF ABI is "intended to use the same structure layout and calling ↵Nicolas Geoffray2007-04-031-66/+19
| | | | | | | | | convention rules as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/). Change all ELF tests to ELF32. llvm-svn: 35624
* Addition to the previous commit for getCalleeSavedRegClasses:Nicolas Geoffray2007-04-031-2/+4
| | | | | | | "The ELF ABI specifies F1-F8 registers as argument registers for double, not F1-F10. This affects only ELF, not MachO." llvm-svn: 35623
* The ELF ABI specifies F1-F8 registers as argument registers for double, notNicolas Geoffray2007-04-031-3/+5
| | | | | | F1-F10. This affects only ELF, not MachO. llvm-svn: 35622
* Protect R31's frame offset from being used by callee-saved registers, when R31Nicolas Geoffray2007-03-211-0/+20
| | | | | | is the frame pointer. llvm-svn: 35233
* Added MRegisterInfo hook to re-materialize an instruction.Evan Cheng2007-03-201-0/+9
| | | | llvm-svn: 35205
* Minor interface change.Evan Cheng2007-03-061-1/+2
| | | | llvm-svn: 34967
* PEI now passes a RegScavenger ptr to eliminateFrameIndex.Evan Cheng2007-02-281-2/+2
| | | | llvm-svn: 34707
* Duplicate use of LR, take 2.Jim Laskey2007-02-271-26/+34
| | | | llvm-svn: 34666
* Backing out Jim's LR spill changes. This was causing llvm-gcc bootstrappingEvan Cheng2007-02-271-11/+2
| | | | | | | | | to infinite loop: PPCMachineFunctionInfo.h updated: 1.2 -> 1.3 PPCRegisterInfo.cpp updated: 1.110 -> 1.111 PPCRegisterInfo.h updated: 1.28 -> 1.29 llvm-svn: 34652
* implement support for the linux/ppc function call ABI. Patch byChris Lattner2007-02-251-11/+116
| | | | | | Nicolas Geoffray! llvm-svn: 34574
* Don't spill LR as a callee saved register.Jim Laskey2007-02-231-2/+11
| | | | llvm-svn: 34533
* By default, spills kills the register being stored.Evan Cheng2007-02-231-15/+15
| | | | llvm-svn: 34515
* Support to provide exception and selector registers.Jim Laskey2007-02-211-1/+8
| | | | llvm-svn: 34482
* Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.Evan Cheng2007-02-191-9/+30
| | | | llvm-svn: 34428
* For PR1207:Reid Spencer2007-02-191-30/+9
| | | | | | | Revert patches that caused the problem. Evan, please investigate and reapply when you've discovered the problem. llvm-svn: 34399
* Added getReservedRegs().Evan Cheng2007-02-171-9/+30
| | | | llvm-svn: 34376
* Support for non-landing pad exception handling.Jim Laskey2007-02-011-0/+4
| | | | llvm-svn: 33755
* Fix CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.llChris Lattner2007-02-011-0/+3
| | | | llvm-svn: 33732
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