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* Temporarily reverting r56683. This is causing a failure during the build of ↵Bill Wendling2008-09-261-1/+0
| | | | | | | | | | | | | | | | | llvm-gcc: /Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311. ../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://developer.apple.com/bugreporter> for instructions. {standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb" {standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression {standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb" ... llvm-svn: 56703
* Fix @llvm.frameaddress codegen. FP elimination optimization should be ↵Evan Cheng2008-09-261-0/+1
| | | | | | disabled when frame address is desired. Also add support for depth > 0. llvm-svn: 56683
* Remove isImm(), isReg(), and friends, in favor of Dan Gohman2008-09-131-2/+2
| | | | | | | | | isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. llvm-svn: 56189
* Trim unnecessary #includes.Dan Gohman2008-07-111-1/+0
| | | | llvm-svn: 53471
* Simplify this use of BuildMI. This is also in preparation forDan Gohman2008-07-071-3/+1
| | | | | | pool-allocating MachineInstrs. llvm-svn: 53198
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-2/+2
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
* Tail call optimization improvements:Arnold Schwaighofer2008-04-301-9/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move platform independent code (lowering of possibly overwritten arguments, check for tail call optimization eligibility) from target X86ISelectionLowering.cpp to TargetLowering.h and SelectionDAGISel.cpp. Initial PowerPC tail call implementation: Support ppc32 implemented and tested (passes my tests and test-suite llvm-test). Support ppc64 implemented and half tested (passes my tests). On ppc tail call optimization is performed if caller and callee are fastcc call is a tail call (in tail call position, call followed by ret) no variable argument lists or byval arguments option -tailcallopt is enabled Supported: * non pic tail calls on linux/darwin * module-local tail calls on linux(PIC/GOT)/darwin(PIC) * inter-module tail calls on darwin(PIC) If constraints are not met a normal call will be emitted. A test checking the argument lowering behaviour on x86-64 was added. llvm-svn: 50477
* Reverse sense of unwind-tables option. This meansDale Johannesen2008-04-141-1/+1
| | | | | | | stack tracebacks on Darwin x86-64 won't work by default; nevertheless, everybody but me thinks this is a good idea. llvm-svn: 49663
* Implement new llc flag -disable-required-unwind-tables.Dale Johannesen2008-04-081-1/+2
| | | | | | Corresponds to -fno-unwind-tables (usually default in gcc). llvm-svn: 49361
* Cosmetic changes per EH patch review feedback.Dale Johannesen2008-04-021-3/+3
| | | | llvm-svn: 49096
* Recommitting EH patch; this should answer most of theDale Johannesen2008-04-021-2/+5
| | | | | | | | | | | | | | | review feedback. -enable-eh is still accepted but doesn't do anything. EH intrinsics use Dwarf EH if the target supports that, and are handled by LowerInvoke otherwise. The separation of the EH table and frame move data is, I think, logically figured out, but either one still causes full EH info to be generated (not sure how to split the metadata correctly). MachineModuleInfo::needsFrameInfo is no longer used and is removed. llvm-svn: 49064
* Revert 49006 for the moment.Dale Johannesen2008-04-011-5/+2
| | | | llvm-svn: 49046
* Emit exception handling info for functions which areDale Johannesen2008-03-311-2/+5
| | | | | | | | | | | not marked nounwind, or for all functions when -enable-eh is set, provided the target supports Dwarf EH. llvm-gcc generates nounwind in the right places; other FEs will need to do so also. Given such a FE, -enable-eh should no longer be needed. llvm-svn: 49006
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-311-9/+0
| | | | llvm-svn: 48995
* detabify llvm, patch by Mike Stump!Chris Lattner2008-03-201-21/+21
| | | | llvm-svn: 48577
* Disable prolog code that aligns the stack when aDale Johannesen2008-03-101-7/+17
| | | | | | | | | | | | | | local object of >16 byte alignment exists. It does not work and getting it to work is not trivial, as explained in the comment. This fixes all the remaining ppc32 failures in the struct-layout-1 part of the gcc testsuite. (gcc does not support this either, and the only way to get such an object is with __attribute__((aligned)) or generic vectors; it can't be done in a standard-conforming program, or with Altivec. So I think disabling it is OK.) llvm-svn: 48188
* Change the "enable/disable" mechanism so that we can enable PPC registerBill Wendling2008-03-101-12/+19
| | | | | | scavenging for 32-bit and 64-bit separately. llvm-svn: 48186
* Add description of individual bits in CR. This fix PR1765.Nicolas Geoffray2008-03-101-32/+65
| | | | llvm-svn: 48143
* Removed spurious EnablePPCRS check.Bill Wendling2008-03-041-4/+3
| | | | llvm-svn: 47918
* Use a command-line option to turn register scavenging on/off for PPC.Bill Wendling2008-03-041-32/+43
| | | | llvm-svn: 47915
* This is the initial check-in for adding register scavenging to PPC. (Currently,Bill Wendling2008-03-031-68/+288
| | | | | | | | | PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that it uses a register other than the default R0 register (the scavenger scrounges for one). A significant part of this patch fixes how kill information is handled. llvm-svn: 47863
* Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR.Chris Lattner2008-02-131-0/+1
| | | | llvm-svn: 47067
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+2
| | | | llvm-svn: 46930
* Remove the nasty LABEL hack with a much less evil one. Now ↵Evan Cheng2008-02-011-10/+0
| | | | | | llvm.dbg.func.start implies a stoppoint is set. SelectionDAGISel records a new source line but does not create a ISD::LABEL node for this special stoppoint. Asm printer will magically print this label. This ensures nothing is emitted before. llvm-svn: 46635
* Add an extra operand to LABEL nodes which distinguishes between debug, EH, ↵Evan Cheng2008-01-311-4/+4
| | | | | | or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution. llvm-svn: 46609
* Makes the same change in ppc backend: avoid inserting prologue before debug ↵Evan Cheng2008-01-311-0/+10
| | | | | | labels. llvm-svn: 46596
* rename MachineInstr::setInstrDescriptor -> setDescChris Lattner2008-01-111-1/+1
| | | | llvm-svn: 45871
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-1/+1
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-2/+1
| | | | llvm-svn: 45680
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-79/+0
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-228/+0
| | | | llvm-svn: 45484
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-28/+0
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-9/+12
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-7/+6
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-4/+4
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Fix a significant code quality regression I introduced on PPC64 quite Chris Lattner2007-12-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a while ago. We now produce: _foo: mflr r0 std r0, 16(r1) ld r2, 16(r1) std r2, 0(r3) ld r0, 16(r1) mtlr r0 blr instead of: _foo: mflr r0 std r0, 16(r1) lis r0, 0 ori r0, r0, 16 ldx r2, r1, r0 std r2, 0(r3) ld r0, 16(r1) mtlr r0 blr for: void foo(void **X) { *X = __builtin_return_address(0); } on ppc64. llvm-svn: 44701
* implement __builtin_return_addr(0) on ppc.Chris Lattner2007-12-081-2/+7
| | | | llvm-svn: 44700
* refactor some code to avoid overloading the name 'usesLR' in Chris Lattner2007-12-081-7/+9
| | | | | | | different places to mean different things. Document what the one in PPCFunctionInfo means and when it is valid. llvm-svn: 44699
* Fix a compilation warning.Evan Cheng2007-12-081-1/+1
| | | | llvm-svn: 44691
* Added canFoldMemoryOperand for PPC.Evan Cheng2007-12-051-0/+20
| | | | llvm-svn: 44623
* Add a argument to storeRegToStackSlot and storeRegToAddr to specify whetherEvan Cheng2007-12-051-13/+15
| | | | | | the stored register is killed. llvm-svn: 44600
* Remove redundant foldMemoryOperand variants and other code clean up.Evan Cheng2007-12-021-2/+5
| | | | llvm-svn: 44517
* Fix a crash on invalid code due to memcpy lowering.Chris Lattner2007-11-271-25/+30
| | | | llvm-svn: 44378
* Add parameter to getDwarfRegNum to permit targetsDale Johannesen2007-11-131-1/+1
| | | | | | | | to use different mappings for EH and debug info; no functional change yet. Fix warning in X86CodeEmitter. llvm-svn: 44056
* Completely forgot, that we have some debug information emission on PPC. This ↵Anton Korobeynikov2007-11-121-2/+2
| | | | | | | | should fix some regressions on ppc nightly tests. llvm-svn: 44029
* Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov2007-11-111-0/+5
| | | | | | | | This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, llvm-svn: 43997
* - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but ↵Evan Cheng2007-10-181-2/+2
| | | | | | | | only returns the opcode of the instruction post unfolding. - Fix some copy+paste bugs. llvm-svn: 43153
* Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister ↵Evan Cheng2007-10-181-6/+6
| | | | | | public interface. llvm-svn: 43150
* Fix a bug handling frame references in ppc inline asm when the frame offsetChris Lattner2007-10-161-24/+33
| | | | | | doesn't fit into 16 bits. llvm-svn: 43032
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