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path: root/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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* Note in PPCFunctionInfo VRSAVE spillsHal Finkel2013-03-231-0/+7
| | | | | | | | | | | | In preparation for using the new register scavenger capability for providing more than one register simultaneously, specifically note functions that have spilled VRSAVE (currently, this can happen only in functions that use the setjmp intrinsic). As with CR spilling, such functions will need to provide two emergency spill slots to the scavenger. No functionality change intended. llvm-svn: 177832
* Improve PPC VR (Altivec) register spillingHal Finkel2013-03-171-0/+8
| | | | | | | | | | | | | | | | This change cleans up two issues with Altivec register spilling: 1. The spilling code was inefficient (using two instructions, and add and a load, when just one would do) 2. The code assumed that r0 would always be available (true for now, but this will change) The new code handles VR spilling just like GPR spills but forced into r+r mode. As a result, when any VR spills are present, we must now always allocate the register-scavenger spill slot. llvm-svn: 177231
* Allocate the RS spill slot for any PPC function with spills and a large ↵Hal Finkel2013-03-151-0/+7
| | | | | | | | | | | | | | | | stack frame For spills into a large stack frame, the FI-elimination code uses the register scavenger to obtain a free GPR for use with an r+r-addressed load or store. When there are no available GPRs, the scavenger gets one by using its spill slot. Previously, we were not always allocating that spill slot and the RS would assert when the spill slot was needed. I don't currently have a small test that triggered the assert, but I've created a small regression test that verifies that the spill slot is now added when the stack frame is sufficiently large. llvm-svn: 177140
* Fix PR14364.Bill Schmidt2013-02-241-1/+8
| | | | | | | | | | | This removes a const_cast hack from PPCRegisterInfo::hasReservedSpillSlot(). The proper place to save the frame index for the CR spill slot is in the PPCFunctionInfo object, not the PPCRegisterInfo object. No new test cases, as this just reimplements existing function. Existing tests such as test/CodeGen/PowerPC/crsave.ll are sufficient. llvm-svn: 175998
* Unweaken vtables as per ↵David Blaikie2011-12-201-1/+2
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Move per-function state out of TargetLowering subclasses and intoDan Gohman2010-04-171-1/+29
| | | | | | MachineFunctionInfo subclasses. llvm-svn: 101634
* Add explicit keywords.Dan Gohman2009-06-051-1/+1
| | | | llvm-svn: 72969
* Rewrite logic to figure out whether LR needs toDale Johannesen2008-10-241-9/+11
| | | | | | | | be saved/restored in the prolog/epilog. We need to do this iff something in the function stores into it. llvm-svn: 58116
* Tail call optimization improvements:Arnold Schwaighofer2008-04-301-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move platform independent code (lowering of possibly overwritten arguments, check for tail call optimization eligibility) from target X86ISelectionLowering.cpp to TargetLowering.h and SelectionDAGISel.cpp. Initial PowerPC tail call implementation: Support ppc32 implemented and tested (passes my tests and test-suite llvm-test). Support ppc64 implemented and half tested (passes my tests). On ppc tail call optimization is performed if caller and callee are fastcc call is a tail call (in tail call position, call followed by ret) no variable argument lists or byval arguments option -tailcallopt is enabled Supported: * non pic tail calls on linux/darwin * module-local tail calls on linux(PIC/GOT)/darwin(PIC) * inter-module tail calls on darwin(PIC) If constraints are not met a normal call will be emitted. A test checking the argument lowering behaviour on x86-64 was added. llvm-svn: 50477
* This is the initial check-in for adding register scavenging to PPC. (Currently,Bill Wendling2008-03-031-2/+10
| | | | | | | | | PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that it uses a register other than the default R0 register (the scavenger scrounges for one). A significant part of this patch fixes how kill information is handled. llvm-svn: 47863
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* implement __builtin_return_addr(0) on ppc.Chris Lattner2007-12-081-4/+18
| | | | llvm-svn: 44700
* refactor some code to avoid overloading the name 'usesLR' in Chris Lattner2007-12-081-1/+5
| | | | | | | different places to mean different things. Document what the one in PPCFunctionInfo means and when it is valid. llvm-svn: 44699
* Duplicate use of LR, take 2.Jim Laskey2007-02-271-0/+7
| | | | llvm-svn: 34666
* Backing out Jim's LR spill changes. This was causing llvm-gcc bootstrappingEvan Cheng2007-02-271-7/+0
| | | | | | | | | to infinite loop: PPCMachineFunctionInfo.h updated: 1.2 -> 1.3 PPCRegisterInfo.cpp updated: 1.110 -> 1.111 PPCRegisterInfo.h updated: 1.28 -> 1.29 llvm-svn: 34652
* Don't spill LR as a callee saved register.Jim Laskey2007-02-231-0/+7
| | | | llvm-svn: 34533
* Add newline at end of file.Reid Spencer2006-11-251-1/+1
| | | | llvm-svn: 31902
* This is a general clean up of the PowerPC ABI. Address several problems andJim Laskey2006-11-161-0/+43
bugs including making sure that the TOS links back to the previous frame, that the maximum call frame size is not included twice when using frame pointers, no longer growing the frame on calls, double storing of SP and a cleaner/faster dynamic alloca. llvm-svn: 31792
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