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* Split foldMemoryOperand into public non-virtual and protected virtualDan Gohman2008-12-031-4/+4
| | | | | | | parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
* Add more const qualifiers. This fixes build breakage from r59540.Dan Gohman2008-11-181-2/+2
| | | | llvm-svn: 59542
* Const-ify several TargetInstrInfo methods.Dan Gohman2008-10-161-4/+4
| | | | llvm-svn: 57622
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-23/+23
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Remove isImm(), isReg(), and friends, in favor of Dan Gohman2008-09-131-4/+4
| | | | | | | | | isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. llvm-svn: 56189
* Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy ↵Owen Anderson2008-08-261-5/+7
| | | | | | | | | requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
* Convert uses of std::vector in TargetInstrInfo to SmallVector. This change ↵Owen Anderson2008-08-141-3/+3
| | | | | | had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-071-47/+55
| | | | | | | | | | | MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
* - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, ↵Evan Cheng2008-07-031-10/+27
| | | | | | | | propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-2/+3
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
* Add option to commuteInstruction() which forces it to create a new ↵Evan Cheng2008-06-161-5/+23
| | | | | | (commuted) instruction. llvm-svn: 52308
* Infrastructure for getting the machine code size of a function and an ↵Nicolas Geoffray2008-04-161-0/+19
| | | | | | instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
* detabify llvm, patch by Mike Stump!Chris Lattner2008-03-201-1/+1
| | | | llvm-svn: 48577
* Change the "enable/disable" mechanism so that we can enable PPC registerBill Wendling2008-03-101-46/+51
| | | | | | scavenging for 32-bit and 64-bit separately. llvm-svn: 48186
* fix 80 col violations.Chris Lattner2008-03-101-8/+8
| | | | llvm-svn: 48166
* Stylistic modifications. No functionality changes.Nicolas Geoffray2008-03-101-44/+39
| | | | llvm-svn: 48158
* Add description of individual bits in CR. This fix PR1765.Nicolas Geoffray2008-03-101-0/+56
| | | | llvm-svn: 48143
* Use a command-line option to turn register scavenging on/off for PPC.Bill Wendling2008-03-041-7/+8
| | | | llvm-svn: 47915
* This is the initial check-in for adding register scavenging to PPC. (Currently,Bill Wendling2008-03-031-31/+54
| | | | | | | | | PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that it uses a register other than the default R0 register (the scavenger scrounges for one). A significant part of this patch fixes how kill information is handled. llvm-svn: 47863
* commuteInstr() can now commute non-ssa machine instrs.Evan Cheng2008-02-131-0/+10
| | | | llvm-svn: 47043
* It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵Evan Cheng2008-02-081-2/+3
| | | | | | the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
* remove MachineOpCode typedef.Chris Lattner2008-01-071-1/+1
| | | | llvm-svn: 45679
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-0/+79
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-0/+230
| | | | llvm-svn: 45484
* Fix a bug in my previous patch: refer to the impl not the pure virtual ↵Chris Lattner2008-01-011-1/+1
| | | | | | version. It's unclear why gcc would ever compile this... llvm-svn: 45476
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-011-1/+1
| | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-0/+28
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-11/+11
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* More cleanups for MachineOperand:Chris Lattner2007-12-301-8/+2
| | | | | | | | | | - Eliminate the static "print" method for operands, moving it into MachineOperand::print. - Change various set* methods for register flags to take a bool for the value to set it to. Remove unset* methods. - Group methods more logically by operand flavor in MachineOperand.h llvm-svn: 45461
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-9/+9
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Add lengthof and endof templates that hide a lot of sizeof computations.Owen Anderson2007-09-071-1/+2
| | | | | | Patch by Sterling Stein! llvm-svn: 41758
* Handle blocks with 2 unconditional branches in AnalyzeBranch.Dale Johannesen2007-06-131-0/+10
| | | | llvm-svn: 37571
* Add a utility routine to check for unpredicated terminator instruction.Evan Cheng2007-06-081-3/+3
| | | | llvm-svn: 37528
* BlockHasNoFallThrough() now returns true if block ends with a return ↵Evan Cheng2007-05-211-0/+1
| | | | | | instruction. llvm-svn: 37266
* RemoveBranch() and InsertBranch() now returns number of instructions deleted ↵Evan Cheng2007-05-181-9/+12
| | | | | | / inserted. llvm-svn: 37192
* Relex assertions to account for additional implicit def / use operands.Evan Cheng2007-04-251-5/+5
| | | | llvm-svn: 36430
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-1/+0
| | | | llvm-svn: 32333
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-5/+5
| | | | | | of opcode and number of operands. llvm-svn: 31947
* convert PPC::BCC to use the 'pred' operand instead of separate predicateChris Lattner2006-11-171-3/+3
| | | | | | | | value and CR reg #. This requires swapping the order of these everywhere that touches BCC and requires us to write custom matching logic for PPCcondbranch :( llvm-svn: 31835
* rename PPC::COND_BRANCH to PPC::BCCChris Lattner2006-11-171-7/+7
| | | | llvm-svn: 31834
* start using PPC predicates more consistently.Chris Lattner2006-11-171-1/+2
| | | | llvm-svn: 31833
* Properly transfer kill / dead info.Evan Cheng2006-11-151-0/+10
| | | | llvm-svn: 31765
* Matches MachineInstr changes.Evan Cheng2006-11-131-1/+1
| | | | llvm-svn: 31712
* implement the BlockHasNoFallThrough hookChris Lattner2006-10-281-0/+11
| | | | llvm-svn: 31264
* Implement support for branch reversal, fix a bug in branch analysis.Chris Lattner2006-10-211-2/+5
| | | | | | | | | | | | | | | | This provides stuff like: cmpw cr0, r15, r29 mr r14, r15 - bge cr0, LBB3_111 ;bb656 - b LBB3_90 ;bb501 + blt cr0, LBB3_90 ;bb501 LBB3_111: ;bb656 lwz r18, 68(r1) which is particularly good for dispatch group formation. llvm-svn: 31101
* Simplify code, no functionality changeChris Lattner2006-10-211-4/+2
| | | | llvm-svn: 31097
* implement support for inserting a cond branchChris Lattner2006-10-211-4/+8
| | | | llvm-svn: 31096
* add support for inserting an uncond branchChris Lattner2006-10-171-2/+8
| | | | llvm-svn: 31003
* implement branch inspection/modification methods.Chris Lattner2006-10-131-0/+93
| | | | llvm-svn: 30946
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