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authorChris Lattner <sabre@nondot.org>2007-12-30 20:49:49 +0000
committerChris Lattner <sabre@nondot.org>2007-12-30 20:49:49 +0000
commit5c4637816e6ff95cd489cb7b6edfcbd70990a772 (patch)
tree64a6f730461f1fea00b3b6dd9c562f4dd8681171 /llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
parent86427bb2a9227fc531383089e494ba5edbe2efda (diff)
downloadbcm5719-llvm-5c4637816e6ff95cd489cb7b6edfcbd70990a772.tar.gz
bcm5719-llvm-5c4637816e6ff95cd489cb7b6edfcbd70990a772.zip
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
llvm-svn: 45453
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.cpp18
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 944d20dac78..b20943ecf1b 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -54,7 +54,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
MI.getOperand(0).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid PPC ADDI instruction!");
- if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
+ if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
@@ -65,7 +65,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid PPC ORI instruction!");
- if (MI.getOperand(2).getImmedValue()==0) {
+ if (MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
@@ -99,7 +99,7 @@ unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
case PPC::LWZ:
case PPC::LFS:
case PPC::LFD:
- if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
+ if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
return MI->getOperand(0).getReg();
@@ -117,7 +117,7 @@ unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
case PPC::STW:
case PPC::STFS:
case PPC::STFD:
- if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
+ if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
return MI->getOperand(0).getReg();
@@ -135,7 +135,7 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
return TargetInstrInfo::commuteInstruction(MI);
// Cannot commute if it has a non-zero rotate count.
- if (MI->getOperand(3).getImmedValue() != 0)
+ if (MI->getOperand(3).getImm() != 0)
return 0;
// If we have a zero rotate count, we have:
@@ -162,10 +162,10 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
MI->getOperand(1).unsetIsKill();
// Swap the mask around.
- unsigned MB = MI->getOperand(4).getImmedValue();
- unsigned ME = MI->getOperand(5).getImmedValue();
- MI->getOperand(4).setImmedValue((ME+1) & 31);
- MI->getOperand(5).setImmedValue((MB-1) & 31);
+ unsigned MB = MI->getOperand(4).getImm();
+ unsigned ME = MI->getOperand(5).getImm();
+ MI->getOperand(4).setImm((ME+1) & 31);
+ MI->getOperand(5).setImm((MB-1) & 31);
return MI;
}
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