Commit message (Collapse) | Author | Age | Files | Lines | |
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* | remove MachineOpCode typedef. | Chris Lattner | 2008-01-07 | 1 | -1/+1 |
| | | | | llvm-svn: 45679 | ||||
* | Move even more functionality from MRegisterInfo into TargetInstrInfo. | Owen Anderson | 2008-01-07 | 1 | -0/+79 |
| | | | | | | Some day I'll get it all moved over... llvm-svn: 45672 | ||||
* | Move some more instruction creation methods from RegisterInfo into InstrInfo. | Owen Anderson | 2008-01-01 | 1 | -0/+230 |
| | | | | llvm-svn: 45484 | ||||
* | Fix a bug in my previous patch: refer to the impl not the pure virtual ↵ | Chris Lattner | 2008-01-01 | 1 | -1/+1 |
| | | | | | | version. It's unclear why gcc would ever compile this... llvm-svn: 45476 | ||||
* | Fix a problem where lib/Target/TargetInstrInfo.h would include and use | Chris Lattner | 2008-01-01 | 1 | -1/+1 |
| | | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475 | ||||
* | Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the | Owen Anderson | 2007-12-31 | 1 | -0/+28 |
| | | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470 | ||||
* | Add new shorter predicates for testing machine operands for various types: | Chris Lattner | 2007-12-30 | 1 | -11/+11 |
| | | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464 | ||||
* | More cleanups for MachineOperand: | Chris Lattner | 2007-12-30 | 1 | -8/+2 |
| | | | | | | | | | | - Eliminate the static "print" method for operands, moving it into MachineOperand::print. - Change various set* methods for register flags to take a bool for the value to set it to. Remove unset* methods. - Group methods more logically by operand flavor in MachineOperand.h llvm-svn: 45461 | ||||
* | Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵ | Chris Lattner | 2007-12-30 | 1 | -9/+9 |
| | | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453 | ||||
* | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner | 2007-12-29 | 1 | -2/+2 |
| | | | | llvm-svn: 45418 | ||||
* | Add lengthof and endof templates that hide a lot of sizeof computations. | Owen Anderson | 2007-09-07 | 1 | -1/+2 |
| | | | | | | Patch by Sterling Stein! llvm-svn: 41758 | ||||
* | Handle blocks with 2 unconditional branches in AnalyzeBranch. | Dale Johannesen | 2007-06-13 | 1 | -0/+10 |
| | | | | llvm-svn: 37571 | ||||
* | Add a utility routine to check for unpredicated terminator instruction. | Evan Cheng | 2007-06-08 | 1 | -3/+3 |
| | | | | llvm-svn: 37528 | ||||
* | BlockHasNoFallThrough() now returns true if block ends with a return ↵ | Evan Cheng | 2007-05-21 | 1 | -0/+1 |
| | | | | | | instruction. llvm-svn: 37266 | ||||
* | RemoveBranch() and InsertBranch() now returns number of instructions deleted ↵ | Evan Cheng | 2007-05-18 | 1 | -9/+12 |
| | | | | | | / inserted. llvm-svn: 37192 | ||||
* | Relex assertions to account for additional implicit def / use operands. | Evan Cheng | 2007-04-25 | 1 | -5/+5 |
| | | | | llvm-svn: 36430 | ||||
* | What should be the last unnecessary <iostream>s in the library. | Bill Wendling | 2006-12-07 | 1 | -1/+0 |
| | | | | llvm-svn: 32333 | ||||
* | Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead | Evan Cheng | 2006-11-27 | 1 | -5/+5 |
| | | | | | | of opcode and number of operands. llvm-svn: 31947 | ||||
* | convert PPC::BCC to use the 'pred' operand instead of separate predicate | Chris Lattner | 2006-11-17 | 1 | -3/+3 |
| | | | | | | | | value and CR reg #. This requires swapping the order of these everywhere that touches BCC and requires us to write custom matching logic for PPCcondbranch :( llvm-svn: 31835 | ||||
* | rename PPC::COND_BRANCH to PPC::BCC | Chris Lattner | 2006-11-17 | 1 | -7/+7 |
| | | | | llvm-svn: 31834 | ||||
* | start using PPC predicates more consistently. | Chris Lattner | 2006-11-17 | 1 | -1/+2 |
| | | | | llvm-svn: 31833 | ||||
* | Properly transfer kill / dead info. | Evan Cheng | 2006-11-15 | 1 | -0/+10 |
| | | | | llvm-svn: 31765 | ||||
* | Matches MachineInstr changes. | Evan Cheng | 2006-11-13 | 1 | -1/+1 |
| | | | | llvm-svn: 31712 | ||||
* | implement the BlockHasNoFallThrough hook | Chris Lattner | 2006-10-28 | 1 | -0/+11 |
| | | | | llvm-svn: 31264 | ||||
* | Implement support for branch reversal, fix a bug in branch analysis. | Chris Lattner | 2006-10-21 | 1 | -2/+5 |
| | | | | | | | | | | | | | | | | This provides stuff like: cmpw cr0, r15, r29 mr r14, r15 - bge cr0, LBB3_111 ;bb656 - b LBB3_90 ;bb501 + blt cr0, LBB3_90 ;bb501 LBB3_111: ;bb656 lwz r18, 68(r1) which is particularly good for dispatch group formation. llvm-svn: 31101 | ||||
* | Simplify code, no functionality change | Chris Lattner | 2006-10-21 | 1 | -4/+2 |
| | | | | llvm-svn: 31097 | ||||
* | implement support for inserting a cond branch | Chris Lattner | 2006-10-21 | 1 | -4/+8 |
| | | | | llvm-svn: 31096 | ||||
* | add support for inserting an uncond branch | Chris Lattner | 2006-10-17 | 1 | -2/+8 |
| | | | | llvm-svn: 31003 | ||||
* | implement branch inspection/modification methods. | Chris Lattner | 2006-10-13 | 1 | -0/+93 |
| | | | | llvm-svn: 30946 | ||||
* | In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones. | Chris Lattner | 2006-07-11 | 1 | -1/+2 |
| | | | | llvm-svn: 29096 | ||||
* | Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file | Chris Lattner | 2006-06-20 | 1 | -1/+1 |
| | | | | llvm-svn: 28889 | ||||
* | Implement the getPointerRegClass method, which is required for the ptr_rc | Chris Lattner | 2006-06-17 | 1 | -3/+13 |
| | | | | | | magic to work. llvm-svn: 28847 | ||||
* | Move some methods out of MachineInstr into MachineOperand | Chris Lattner | 2006-05-04 | 1 | -2/+2 |
| | | | | llvm-svn: 28102 | ||||
* | teach the ppc backend how to spill/reload vector regs | Chris Lattner | 2006-03-16 | 1 | -1/+1 |
| | | | | llvm-svn: 26806 | ||||
* | Add support for copying registers. still needed: spilling and reloading them | Chris Lattner | 2006-03-16 | 1 | -1/+1 |
| | | | | llvm-svn: 26800 | ||||
* | implement TII::insertNoop | Chris Lattner | 2006-03-05 | 1 | -0/+5 |
| | | | | llvm-svn: 26562 | ||||
* | add 64b gpr store to the possible list of isStoreToStackSlot opcodes. | Nate Begeman | 2006-02-02 | 1 | -1/+1 |
| | | | | llvm-svn: 25916 | ||||
* | implement isStoreToStackSlot for PPC | Chris Lattner | 2006-02-02 | 1 | -1/+18 |
| | | | | llvm-svn: 25914 | ||||
* | Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far ↵ | Chris Lattner | 2006-02-02 | 1 | -0/+19 |
| | | | | | | more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913 | ||||
* | teach ppc backend these are copies | Chris Lattner | 2005-10-19 | 1 | -1/+2 |
| | | | | llvm-svn: 23813 | ||||
* | First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is | Nate Begeman | 2005-10-18 | 1 | -1/+1 |
| | | | | | | purely mechanical. llvm-svn: 23778 | ||||
* | More PPC32 -> PPC changes, as well as merging some classes that were | Nate Begeman | 2005-10-16 | 1 | -6/+6 |
| | | | | | | redundant after the change. llvm-svn: 23759 | ||||
* | Rename PPC32*.h to PPC*.h | Chris Lattner | 2005-10-14 | 1 | -0/+111 |
This completes the grand PPC file renaming llvm-svn: 23745 |