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* Fix PR11985Michael Liao2012-09-121-2/+2
| | | | | | | | | | | - BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. llvm-svn: 163743
* PPCISelLowering.cpp: Fix r162725.NAKAMURA Takumi2012-08-301-1/+5
| | | | | | | | [Tobias von Koch] What's happening here is that the CR6SET/CR6UNSET is breaking the chain of register copies glued to the function call (BL_SVR4 node). The scheduler then moves other instructions in between those and the function call, which isn't good! Right. That's the case where there is no chain of register copies before the call, so InFlag == 0... Attached is a new revision of the patch which should fix this for good. llvm-svn: 162916
* PPCISelLowering.cpp: Whitespace.NAKAMURA Takumi2012-08-301-1/+1
| | | | llvm-svn: 162915
* Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel2012-08-281-0/+15
| | | | | | | | | Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. llvm-svn: 162764
* Eliminate redundant CR moves on PPC32.Hal Finkel2012-08-281-8/+14
| | | | | | | | | | | | | | | | The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and unset if it doesn't. The solution up to now was to insert a MachineNode to set/unset the CR bit, which produces a CR vreg. This vreg was then copied into CR bit 6. When the register allocator saw a bunch of these in the same function, it allocated the set/unset CR bit in some random CR register (1 extra instruction) and then emitted CR moves before every vararg function call, rather than just setting and unsetting CR bit 6 directly before every vararg function call. This patch instead inserts a PPCcrset/PPCcrunset instruction which are then matched by a dedicated instruction pattern. Patch by Tobias von Koch. llvm-svn: 162725
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-241-8/+7
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Lower constant pools and jump tables via TOC on PPC64/SVR4.Roman Divacky2012-08-241-0/+16
| | | | | | In collaboration with Adhemerval Zanella. llvm-svn: 162562
* Fix typo and grammar. By Adhemerval Zanella.Roman Divacky2012-08-161-1/+1
| | | | llvm-svn: 162032
* Add readcyclecounter lowering on PPC64.Hal Finkel2012-08-041-1/+3
| | | | | | | | On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. llvm-svn: 161302
* Target option DisableJumpTables is a gross hack. Move it to TargetLowering ↵Evan Cheng2012-07-021-10/+17
| | | | | | instead. llvm-svn: 159611
* Add support for the PPC isel instruction.Hal Finkel2012-06-221-5/+31
| | | | | | | The isel (integer select) instruction is supported on the 440 and A2 embedded cores and on the POWER7. llvm-svn: 159045
* Convert the PPC backend to use the new FMA infrastructure.Hal Finkel2012-06-221-2/+23
| | | | | | | The existing contraction patterns are replaced with fma/fneg. Overall functionality should be the same. llvm-svn: 158955
* Add support for generating reg+reg (indexed) pre-inc loads on PPC.Hal Finkel2012-06-201-7/+2
| | | | llvm-svn: 158823
* Add support for generating reg+reg preinc stores on PPC.Hal Finkel2012-06-191-1/+9
| | | | | | PPC will now generate STWUX and friends. llvm-svn: 158698
* Enable ILP scheduling for all nodes by default on PPC.Hal Finkel2012-06-101-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | Over the entire test-suite, this has an insignificantly negative average performance impact, but reduces some of the worst slowdowns from the anti-dep. change (r158294). Largest speedups: SingleSource/Benchmarks/Stanford/Quicksort - 28% SingleSource/Benchmarks/Stanford/Towers - 24% SingleSource/Benchmarks/Shootout-C++/matrix - 23% MultiSource/Benchmarks/SciMark2-C/scimark2 - 19% MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - 15% (matrix and automotive-bitcount were both in the top-5 slowdown list from the anti-dep. change) Largest slowdowns: MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28% MultiSource/Benchmarks/mediabench/gsm/toast/toast - 26% MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan - 21% SingleSource/Benchmarks/CoyoteBench/lpbench - 20% MultiSource/Applications/d/make_dparser - 16% llvm-svn: 158296
* PPC32 uses R2 as the TLS register. Fix the copy and paste.Roman Divacky2012-06-051-3/+3
| | | | llvm-svn: 158004
* Implement local-exec TLS on PowerPC.Roman Divacky2012-06-041-1/+26
| | | | llvm-svn: 157935
* Enable generating PPC pre-increment (r+imm) instructions by default.Hal Finkel2012-06-041-5/+3
| | | | | | | It seems that this no longer causes test suite failures on PPC64 (after r157159), and often gives a performance benefit, so it can be enabled by default. llvm-svn: 157911
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-251-11/+19
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* effectively back out my last change (r155190)Gabor Greif2012-04-201-2/+2
| | | | llvm-svn: 155195
* fix obviously bogus (IMO) operand index of the load in assertsGabor Greif2012-04-201-3/+3
| | | | | | | | | (load only has one operand) and smuggle in some whitespace changes too NB: I am obviously testing the water here, and believe that the unguarded cast is still wrong, but why is the getZExtValue of the load's operand tested against zero here? Any review is appreciated. llvm-svn: 155190
* Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-19/+19
| | | | | | since they are equivalent. llvm-svn: 155186
* zap tabsGabor Greif2012-04-191-7/+7
| | | | llvm-svn: 155128
* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-041-14/+3
| | | | | | | | This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
* Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.Roman Divacky2012-04-021-1/+10
| | | | llvm-svn: 153876
* Enable prefetch generation on PPC64.Hal Finkel2012-04-011-0/+3
| | | | llvm-svn: 153851
* Set the default PPC node scheduling preference to ILP (for the embedded cores).Hal Finkel2012-04-011-0/+9
| | | | | | | The 440 and A2 cores have detailed itineraries, and this allows them to be fully used to maximize throughput. llvm-svn: 153845
* Fix dynamic linking on PPC64.Hal Finkel2012-03-311-8/+15
| | | | | | | | | | | | | | | | | | Dynamic linking on PPC64 has had problems since we had to move the top-down hazard-detection logic post-ra. For dynamic linking to work there needs to be a nop placed after every call. It turns out that it is really hard to guarantee that nothing will be placed in between the call (bl) and the nop during post-ra scheduling. Previous attempts at fixing this by placing logic inside the hazard detector only partially worked. This is now fixed in a different way: call+nop codegen-only instructions. As far as CodeGen is concerned the pair is now a single instruction and cannot be split. This solution works much better than previous attempts. The scoreboard hazard detector is also renamed to be more generic, there is currently no cpu-specific logic in it. llvm-svn: 153816
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-1/+1
| | | | llvm-svn: 153500
* Fix small-integer VAARG on SVR4 ABI PPC64.Hal Finkel2012-03-241-5/+17
| | | | | | | The PPC64 SVR4 ABI requires integer stack arguments, and thus the var. args., that are smaller than 64 bits be zero extended to 64 bits. llvm-svn: 153373
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-7/+7
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Convert more static tables of registers used by calling convention to ↵Craig Topper2012-03-111-4/+4
| | | | | | uint16_t to reduce space. llvm-svn: 152538
* Use uint16_t to store registers and opcode in static tables in the target ↵Craig Topper2012-03-111-12/+12
| | | | | | specific backends. llvm-svn: 152537
* Convert PowerPC to register mask operands.Roman Divacky2012-03-061-0/+6
| | | | llvm-svn: 152122
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-281-3/+4
| | | | | | direct call. llvm-svn: 151645
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-281-4/+3
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-3/+4
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-1/+1
| | | | | | to static data that should not be modified. llvm-svn: 151134
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-2/+1
| | | | llvm-svn: 149961
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+0
| | | | llvm-svn: 148578
* Remove a bunch of unused variable assignments.Benjamin Kramer2012-01-201-2/+1
| | | | | | Found by the clang static analyzer. llvm-svn: 148541
* Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through ↵Benjamin Kramer2012-01-151-2/+1
| | | | | | CodeGen. llvm-svn: 148218
* Remove VectorExtras. This unused helper was written for a type of API that ↵Benjamin Kramer2012-01-071-1/+0
| | | | | | is discouraged now. llvm-svn: 147738
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
* Teach SelectionDAG to match more calls to libm functions onto existing ↵Owen Anderson2011-12-081-0/+7
| | | | | | SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. llvm-svn: 146171
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-10/+16
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* add basic PPC register-pressure feedback; adjust the vaarg test to match the ↵Hal Finkel2011-11-221-0/+2
| | | | | | new register-allocation pattern llvm-svn: 145065
* Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad2011-11-151-1/+0
| | | | llvm-svn: 144631
* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-081-21/+26
| | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
* Rename NonScalarIntSafe to something more appropriate.Lang Hames2011-10-261-2/+2
| | | | llvm-svn: 143080
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