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path: root/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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* Use tblgen'd VECTOR_SHUFFLE selection code.Evan Cheng2006-03-201-16/+0
| | | | llvm-svn: 26900
* Add support for generating vspltw, instead of a vperm instruction with aChris Lattner2006-03-201-0/+16
| | | | | | | | constant pool load. This generates significantly nicer code for splats. When tblgen gets bugfixed, we can remove the custom selection code. llvm-svn: 26898
* Remove BRTWOWAY*Nate Begeman2006-03-171-34/+4
| | | | | | | | Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. llvm-svn: 26814
* Save/restore VRSAVE once per function, not once per block.Chris Lattner2006-03-161-39/+52
| | | | llvm-svn: 26793
* Fix an off by one error that caused PPC LLC failures last night.Chris Lattner2006-03-141-1/+1
| | | | llvm-svn: 26758
* Added getTargetLowering() to TargetMachine. Refactored targets to support this.Evan Cheng2006-03-131-3/+4
| | | | llvm-svn: 26742
* For functions that use vector registers, save VRSAVE, mark usedChris Lattner2006-03-131-1/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | registers, and update it on entry to each function, then restore it on exit. This compiles: void func(vfloat *a, vfloat *b, vfloat *c) { *a = *b * *c + *c; } to this: _func: mfspr r2, 256 oris r6, r2, 49152 mtspr 256, r6 lvx v0, 0, r5 lvx v1, 0, r4 vmaddfp v0, v1, v0, v0 stvx v0, 0, r3 mtspr 256, r2 blr GCC produces this (which has additional stack accesses): _func: mfspr r0,256 stw r0,-4(r1) oris r0,r0,0xc000 mtspr 256,r0 lvx v0,0,r5 lvx v1,0,r4 lwz r12,-4(r1) vmaddfp v0,v0,v1,v0 stvx v0,0,r3 mtspr 256,r12 blr llvm-svn: 26733
* Several big changes:Chris Lattner2006-03-121-1/+3
| | | | | | | | | | | 1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. llvm-svn: 26719
* Change the interface for getting a target HazardRecognizer to be more clean.Chris Lattner2006-03-081-4/+3
| | | | llvm-svn: 26608
* Implement a very very simple hazard recognizer for LSU rejects and ctr set/readChris Lattner2006-03-071-2/+10
| | | | | | flushes llvm-svn: 26587
* Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.Chris Lattner2006-03-011-18/+59
| | | | llvm-svn: 26450
* Implement selection of inline asm memory operandsChris Lattner2006-02-241-0/+29
| | | | llvm-svn: 26348
* kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBCNate Begeman2006-02-171-75/+0
| | | | | | | and SUBE nodes that actually expose what's going on and allow for significant simplifications in the targets. llvm-svn: 26255
* If the false case is the current basic block, then this is a self loop.Evan Cheng2006-02-161-11/+0
| | | | | | | | | | We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra instruction in the loop. Instead, invert the condition and emit "Loop: ... br!cond Loop; br Out. Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering. llvm-svn: 26231
* Match getTargetNode() changes (now return SDNode* instead of SDOperand).Evan Cheng2006-02-091-68/+79
| | | | llvm-svn: 26085
* Change Select() fromEvan Cheng2006-02-091-80/+133
| | | | | | | | SDOperand Select(SDOperand N); to void Select(SDOperand &Result, SDOperand N); llvm-svn: 26067
* Complex pattern isel code shouldn't select nodes.Evan Cheng2006-02-051-9/+9
| | | | llvm-svn: 26010
* Use SelectRoot() as entry of any tblgen based isel.Evan Cheng2006-02-051-1/+2
| | | | llvm-svn: 25997
* Use PPCISD::CALL instead of ISD::CALLChris Lattner2006-01-271-2/+1
| | | | llvm-svn: 25717
* Add explicit #includes of <iostream>Chris Lattner2006-01-221-0/+1
| | | | llvm-svn: 25515
* Use the default impl of DYNAMIC_STACKALLOC, allowing us to delete some code.Chris Lattner2006-01-151-38/+0
| | | | llvm-svn: 25334
* these cases are autogeneratedChris Lattner2006-01-121-28/+0
| | | | llvm-svn: 25238
* remove dead codeChris Lattner2006-01-121-25/+2
| | | | llvm-svn: 25237
* Fix a compile crash building MultiSource/Applications/d with the new front-end.Chris Lattner2006-01-051-2/+2
| | | | | | | The PPC backend was generating random shift counts in this case, due to an uninitialized variable. llvm-svn: 25114
* Fix one of the things in the todo file, and get a bit closer to foldingNate Begeman2005-12-241-1/+15
| | | | | | constant offsets from statics into the address arithmetic. llvm-svn: 24999
* Pattern-match return. Includes gross hack!Nate Begeman2005-12-201-23/+0
| | | | llvm-svn: 24874
* Fix a couple of the FIXMEs, thanks to suggestion from Chris. This allowsNate Begeman2005-12-191-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | us to load and store vectors directly at a pointer (offset of zero) by using r0 as the base register. This also requires some asm printer work to satisfy the darwin assembler. For void %foo(<4 x float> * %a) { entry: %tmp1 = load <4 x float> * %a; %tmp2 = add <4 x float> %tmp1, %tmp1 store <4 x float> %tmp2, <4 x float> *%a ret void } We now produce: _foo: lvx v0, 0, r3 vaddfp v0, v0, v0 stvx v0, 0, r3 blr Instead of: _foo: li r2, 0 lvx v0, r2, r3 vaddfp v0, v0, v0 stvx v0, r2, r3 blr llvm-svn: 24872
* Convert load/store over to being pattern matchedNate Begeman2005-12-191-145/+71
| | | | llvm-svn: 24871
* This is handled by the autogen'd codeChris Lattner2005-12-181-1/+0
| | | | llvm-svn: 24834
* Remove a now unused statistic.Nate Begeman2005-12-141-1/+0
| | | | llvm-svn: 24720
* Use the new predicate support that Evan Cheng added to remove some codeNate Begeman2005-12-141-47/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | from the DAGToDAG cpp file. This adds pattern support for vector and scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and does the right thing in the presence of -disable-excess-fp-precision. Allows us to match: void %foo(<4 x float> * %a) { entry: %tmp1 = load <4 x float> * %a; %tmp2 = mul <4 x float> %tmp1, %tmp1 %tmp3 = add <4 x float> %tmp2, %tmp1 store <4 x float> %tmp3, <4 x float> *%a ret void } As: _foo: li r2, 0 lvx v0, r2, r3 vmaddfp v0, v0, v0, v0 stvx v0, r2, r3 blr Or, with llc -disable-excess-fp-precision, _foo: li r2, 0 lvx v0, r2, r3 vxor v1, v1, v1 vmaddfp v1, v0, v0, v1 vaddfp v0, v1, v0 stvx v0, r2, r3 blr llvm-svn: 24719
* Add support for TargetConstantPool nodes to the dag isel emitter, and useNate Begeman2005-12-101-24/+5
| | | | | | | them in the PPC backend, to simplify some logic out of Select and SelectAddr. llvm-svn: 24657
* Silence another annoying GCC warningChris Lattner2005-12-061-1/+1
| | | | llvm-svn: 24627
* The basic fneg cases are already autogen'dChris Lattner2005-12-041-4/+2
| | | | llvm-svn: 24592
* Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgenChris Lattner2005-12-041-8/+0
| | | | | | improvements. llvm-svn: 24591
* Finish moving uncond br over to .td file, remove from .cpp file.Chris Lattner2005-12-041-3/+1
| | | | llvm-svn: 24590
* Make sure these get added into the codegenmap when appropriateChris Lattner2005-12-011-4/+5
| | | | llvm-svn: 24566
* Fix a regression caused by a patch earlier todayChris Lattner2005-12-011-1/+2
| | | | llvm-svn: 24561
* Use a getCopyToReg() variant to generate a flaggy CopyToReg node.Evan Cheng2005-12-011-8/+2
| | | | llvm-svn: 24558
* SelectNodeTo now returns N. Use it instead of return N directly.Chris Lattner2005-11-301-108/+81
| | | | llvm-svn: 24549
* First chunk of actually generating vector code for packed types. TheseNate Begeman2005-11-301-11/+51
| | | | | | | | | | | | | | | | | | | | | | | changes allow us to generate the following code: _foo: li r2, 0 lvx v0, r2, r3 vaddfp v0, v0, v0 stvx v0, r2, r3 blr for this llvm: void %foo(<4 x float>* %a) { entry: %tmp1 = load <4 x float>* %a %tmp2 = add <4 x float> %tmp1, %tmp1 store <4 x float> %tmp2, <4 x float>* %a ret void } llvm-svn: 24534
* Enable global address legalization, fixing a todo and allowing the removalChris Lattner2005-11-171-30/+1
| | | | | | | | of some code. This exposes the implicit load from the stubs to the DAG, allowing them to be optimized by the dag combiner. It also moves darwin specific stuff out of the isel into the legalizer, and allows more to be moved to the .td file. llvm-svn: 24397
* Teach the selector to fold lo(g) into load instruction immediate fieldsChris Lattner2005-11-171-0/+8
| | | | llvm-svn: 24396
* Add an initial hack at legalizing GlobalAddress into the appropriate nodesChris Lattner2005-11-171-1/+4
| | | | | | | | | | | | | | | | on Darwin to remove smarts from the isel. This is currently disabled by default (uncomment setOperationAction(ISD::GlobalAddress to enable it). tblgen needs to become smarter about tglobaladdr nodes and bigger patterns needed to be added to the .td file. However, we can currently emit stuff like this: :) li r2, lo16(L_x$non_lazy_ptr) lis r3, ha16(L_x$non_lazy_ptr) lwzx r2, r3, r2 The obvious improvements will follow. llvm-svn: 24390
* When lowering direct calls, lower them to use a targetglobaladress directlyChris Lattner2005-11-171-2/+1
| | | | | | instead of a globaladdress. This has no effect on the generated code at all. llvm-svn: 24386
* Patch to clean up function call pseudos and support the BLA instruction,Nate Begeman2005-11-161-6/+17
| | | | | | | which branches to an absolute address. This is required to support objc direct dispatch. llvm-svn: 24370
* Don't emit "32" for unordered comparisonChris Lattner2005-10-281-2/+4
| | | | llvm-svn: 24073
* add a hack to get code with ordered comparisons working. This hack isChris Lattner2005-10-281-12/+12
| | | | | | tracked as PR642 llvm-svn: 24068
* add support for branch on ordered/unordered.Chris Lattner2005-10-281-0/+17
| | | | llvm-svn: 24067
* autogen undefChris Lattner2005-10-251-8/+0
| | | | llvm-svn: 23991
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