Use the new predicate support that Evan Cheng added to remove some code

from the DAGToDAG cpp file.  This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.

Allows us to match:
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  %tmp3 = add <4 x float> %tmp2, %tmp1
  store <4 x float> %tmp3, <4 x float> *%a
  ret void
}

As:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vmaddfp v0, v0, v0, v0
        stvx v0, r2, r3
        blr

Or, with llc -disable-excess-fp-precision,

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v1, v0, v0, v1
        vaddfp v0, v1, v0
        stvx v0, r2, r3
        blr

llvm-svn: 24719

1 files changed, 0 insertions, 47 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 01d089d9b91..f666f232556 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -885,53 +885,6 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
                             CurDAG->getTargetFrameIndex(FI, MVT::i32),
                             getI32Imm(0));
   }
-  case ISD::FADD: {
-    MVT::ValueType Ty = N->getValueType(0);
-    if (!NoExcessFPPrecision) {  // Match FMA ops
-      if (N->getOperand(0).getOpcode() == ISD::FMUL &&
-          N->getOperand(0).Val->hasOneUse()) {
-        ++FusedFP; // Statistic
-        return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD :PPC::FMADDS,
-                                    Ty, Select(N->getOperand(0).getOperand(0)),
-                                    Select(N->getOperand(0).getOperand(1)),
-                                    Select(N->getOperand(1)));
-      } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
-                 N->getOperand(1).hasOneUse()) {
-        ++FusedFP; // Statistic
-        return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD :PPC::FMADDS,
-                                    Ty, Select(N->getOperand(1).getOperand(0)),
-                                    Select(N->getOperand(1).getOperand(1)),
-                                    Select(N->getOperand(0)));
-      }
-    }
-    
-    // Other cases are autogenerated.
-    break;
-  }
-  case ISD::FSUB: {
-    MVT::ValueType Ty = N->getValueType(0);
-    
-    if (!NoExcessFPPrecision) {  // Match FMA ops
-      if (N->getOperand(0).getOpcode() == ISD::FMUL &&
-          N->getOperand(0).Val->hasOneUse()) {
-        ++FusedFP; // Statistic
-        return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB:PPC::FMSUBS,
-                                    Ty, Select(N->getOperand(0).getOperand(0)),
-                                    Select(N->getOperand(0).getOperand(1)),
-                                    Select(N->getOperand(1)));
-      } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
-                 N->getOperand(1).Val->hasOneUse()) {
-        ++FusedFP; // Statistic
-        return CurDAG->SelectNodeTo(N, Ty == MVT::f64 ?PPC::FNMSUB:PPC::FNMSUBS, 
-                                    Ty, Select(N->getOperand(1).getOperand(0)),
-                                    Select(N->getOperand(1).getOperand(1)),
-                                    Select(N->getOperand(0)));
-      }
-    }
-
-    // Other cases are autogenerated.
-    break;
-  }
   case ISD::SDIV: {
     // FIXME: since this depends on the setting of the carry flag from the srawi
     //        we should really be making notes about that for the scheduler.