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* add patterns for ppc32 preinc stores. ppc64 next.Chris Lattner2006-11-161-0/+8
| | | | llvm-svn: 31775
* fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memriChris Lattner2006-11-151-27/+28
| | | | | | addrmodes. llvm-svn: 31757
* remove a ton of custom selection logic no longer neededChris Lattner2006-11-141-145/+7
| | | | llvm-svn: 31733
* allow the offset of a preinc'd load to be the low-part of a global. ThisChris Lattner2006-11-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | produces this clever code: _millisecs: lis r2, ha16(_Time.1182) lwzu r3, lo16(_Time.1182)(r2) lwz r2, 4(r2) addic r4, r2, 1 addze r3, r3 blr instead of this: _millisecs: lis r2, ha16(_Time.1182) la r3, lo16(_Time.1182)(r2) lwz r2, lo16(_Time.1182)(r2) lwz r3, 4(r3) addic r4, r3, 1 addze r3, r2 blr for: long %millisecs() { %tmp = load long* %Time.1182 ; <long> [#uses=1] %tmp1 = add long %tmp, 1 ; <long> [#uses=1] ret long %tmp1 } llvm-svn: 31673
* implement preinc support for r+i loads on ppc64Chris Lattner2006-11-101-8/+23
| | | | llvm-svn: 31654
* add an initial cut at preinc loads for ppc32. This is broken for ppc64Chris Lattner2006-11-101-0/+38
| | | | | | | | | (because the 64-bit reg target versions aren't implemented yet), doesn't support r+r addr modes, and doesn't handle stores, but it works otherwise. :) This is disabled unless -enable-ppc-preinc is passed to llc for now. llvm-svn: 31621
* Match tblegen changes.Evan Cheng2006-11-081-9/+12
| | | | llvm-svn: 31571
* Refactor all the addressing mode selection stuff into the isel loweringChris Lattner2006-11-081-228/+13
| | | | | | class, where it can be used for preinc formation. llvm-svn: 31536
* For PR786:Reid Spencer2006-11-021-2/+0
| | | | | | | | | | Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting fall out by removing unused variables. Remaining warnings have to do with unused functions (I didn't want to delete code without review) and unused variables in generated code. Maintainers should clean up the remaining issues when they see them. All changes pass DejaGnu tests and Olden. llvm-svn: 31380
* fix miscompilation of llvm.isunordered, where we branched on the oppositeChris Lattner2006-10-301-2/+2
| | | | | | condition. This fixes miscompilation of Olden/bh and many others. llvm-svn: 31301
* Fold AND and ROTL more oftenNate Begeman2006-09-221-28/+38
| | | | llvm-svn: 30577
* Improve PPC64 equality comparisons like PPC32 comparisons.Chris Lattner2006-09-201-3/+31
| | | | llvm-svn: 30510
* Two improvements:Chris Lattner2006-09-201-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Codegen this comparison: if (X == 0x8000) as: cmplwi cr0, r3, 32768 bne cr0, LBB1_2 ;cond_next instead of: lis r2, 0 ori r2, r2, 32768 cmpw cr0, r3, r2 bne cr0, LBB1_2 ;cond_next 2. Codegen this comparison: if (X == 0x12345678) as: xoris r2, r3, 4660 cmplwi cr0, r2, 22136 bne cr0, LBB1_2 ;cond_next instead of: lis r2, 4660 ori r2, r2, 22136 cmpw cr0, r3, r2 bne cr0, LBB1_2 ;cond_next llvm-svn: 30509
* s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|Chris Lattner2006-08-271-1/+1
| | | | llvm-svn: 29911
* Do not use getTargetNode() and SelectNodeTo() which takes more than 3Evan Cheng2006-08-271-43/+41
| | | | | | SDOperand arguments. Use the variants which take an array and number instead. llvm-svn: 29907
* SelectNodeTo now returns a SDNode*.Evan Cheng2006-08-261-20/+20
| | | | llvm-svn: 29901
* Select() no longer require Result operand by reference.Evan Cheng2006-08-261-10/+8
| | | | llvm-svn: 29898
* Match tblgen changes.Evan Cheng2006-08-261-53/+68
| | | | llvm-svn: 29895
* Fix PowerPC/2006-08-15-SelectionCrash.ll and simplify selection code.Chris Lattner2006-08-151-93/+63
| | | | llvm-svn: 29715
* Match tablegen changes.Evan Cheng2006-08-111-53/+32
| | | | llvm-svn: 29604
* Start eliminating temporary vectors used to create DAG nodes. Instead, passChris Lattner2006-08-081-7/+11
| | | | | | | | | | | | | | | | | | | in the start of an array and a count of operands where applicable. In many cases, the number of operands is known, so this static array can be allocated on the stack, avoiding the heap. In many other cases, a SmallVector can be used, which has the same benefit in the common cases. I updated a lot of code calling getNode that takes a vector, but ran out of time. The rest of the code should be updated, and these methods should be removed. We should also do the same thing to eliminate the methods that take a vector of MVT::ValueTypes. It would be extra nice to convert the dagiselemitter to avoid creating vectors for operands when calling getTargetNode. llvm-svn: 29566
* Match tablegen isel changes.Evan Cheng2006-08-071-101/+50
| | | | llvm-svn: 29549
* Remove InFlightSet hack. No longer needed.Evan Cheng2006-07-281-1/+0
| | | | llvm-svn: 29373
* Remove NodeDepthEvan Cheng2006-07-271-6/+1
| | | | llvm-svn: 29338
* shrink libllvmgcc.dylib another 25KChris Lattner2006-06-281-1/+2
| | | | llvm-svn: 28971
* Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)Chris Lattner2006-06-271-4/+5
| | | | llvm-svn: 28944
* Fix ppc64 jump tablesChris Lattner2006-06-271-1/+2
| | | | llvm-svn: 28941
* Fix variable shadowing issueChris Lattner2006-06-271-2/+1
| | | | llvm-svn: 28922
* Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (butChris Lattner2006-06-271-111/+192
| | | | | | doesn't work right). llvm-svn: 28921
* Work around a nasty tblgen bug where it doesn't add operands for varargsChris Lattner2006-06-101-0/+157
| | | | | | nodes correctly. llvm-svn: 28745
* Fix build failure of povrayChris Lattner2006-05-251-0/+2
| | | | llvm-svn: 28473
* Fix Benchmarks/MallocBench/cfracChris Lattner2006-05-251-0/+2
| | | | llvm-svn: 28471
* Assert if InflightSet is not cleared after instruction selecting a BB.Evan Cheng2006-05-251-0/+1
| | | | llvm-svn: 28459
* Clear HandleMap and ReplaceMap after instruction selection. Or it may causeEvan Cheng2006-05-241-0/+2
| | | | | | non-deterministic behavior. llvm-svn: 28454
* Make PPC call lowering more aggressive, making the isel matching code simpleChris Lattner2006-05-171-64/+0
| | | | | | enough to be autogenerated. llvm-svn: 28354
* Switch PPC over to a call-selection model where the lowering code createsChris Lattner2006-05-171-99/+25
| | | | | | | | the copyto/fromregs instead of making the PPCISD::CALL selection code create them. This vastly simplifies the selection code, and moves the ABI handling parts into one place. llvm-svn: 28346
* implement passing/returning vector regs to calls, at least non-varargs calls.Chris Lattner2006-05-161-28/+42
| | | | llvm-svn: 28341
* Fix PowerPC/2006-05-12-rlwimi-crash.llChris Lattner2006-05-121-3/+4
| | | | | | | Nate, please verify that if InsertMask is 0, rlwimi shouldn't be used. This fixes the crash and causes no PPC testsuite regressions. llvm-svn: 28243
* Fold more shifts into inserts, and update the READMENate Begeman2006-05-081-16/+23
| | | | llvm-svn: 28168
* Update some stuff now that the new rlwimi code has gone inNate Begeman2006-05-081-1/+0
| | | | llvm-svn: 28162
* New rlwimi implementation, which is superior to the old one. There areNate Begeman2006-05-071-86/+45
| | | | | | | | still a couple missed optimizations, but we now generate all the possible rlwimis for multiple inserts into the same bitfield. More regression tests to come. llvm-svn: 28156
* JumpTable support! What this represents is working asm and jit support forNate Begeman2006-04-221-2/+13
| | | | | | | | x86 and ppc for 100% dense switch statements when relocations are non-PIC. This support will be extended and enhanced in the coming days to support PIC, and less dense forms of jump tables. llvm-svn: 27947
* Add VRRC select supportChris Lattner2006-04-081-1/+4
| | | | llvm-svn: 27543
* Codegen vector predicate compares.Chris Lattner2006-03-261-0/+14
| | | | llvm-svn: 27151
* #include Intrinsics.h into all dag iselsChris Lattner2006-03-251-0/+1
| | | | llvm-svn: 27109
* Like the comment says, prefer to use the implicit add done by [r+r] addressingChris Lattner2006-03-241-4/+14
| | | | | | | modes than emitting an explicit add and using a base of r0. This implements Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll llvm-svn: 27068
* Add support for "ri" addressing modes where the immediate is a 14-bit fieldChris Lattner2006-03-221-0/+81
| | | | | | | which is shifted left two bits before use. Instructions like STD use this addressing mode. llvm-svn: 26942
* With Evan's latest tblgen patch, this code is obsolete, thanks Evan!Chris Lattner2006-03-211-16/+0
| | | | llvm-svn: 26917
* Handle constant addresses more efficiently, folding the low bits into theChris Lattner2006-03-201-0/+17
| | | | | | | | | | | | | | | | | | | | disp field of the load/store if possible. This compiles CodeGen/PowerPC/load-constant-addr.ll to: _test: lis r2, 2838 lfs f1, 26848(r2) blr instead of: _test: lis r2, 2838 ori r2, r2, 26848 lfs f1, 0(r2) blr llvm-svn: 26908
* reenable this hack, the tblgen version isn't quite readyChris Lattner2006-03-201-0/+16
| | | | llvm-svn: 26902
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