Codegen vector predicate compares.

llvm-svn: 27151

1 files changed, 14 insertions, 0 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 8e5cff798f9..4e74b2c639d 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -1060,6 +1060,20 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                                       getI32Imm(0)), 0);
     return;
   }
+
+  case PPCISD::MFCR: {
+    SDOperand InFlag;
+    Select(InFlag, N->getOperand(1));
+    // Use MFOCRF if supported.
+    if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
+      Result = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
+                                               N->getOperand(0), InFlag), 0);
+    else
+      Result = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag), 0);
+    CodeGenMap[Op] = Result;
+    return;
+  }
+    
   case ISD::SDIV: {
     // FIXME: since this depends on the setting of the carry flag from the srawi
     //        we should really be making notes about that for the scheduler.