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* PR12716: PPC crashes on vector compareAdhemerval Zanella2012-10-081-2/+21
| | | | | | | | | | | | | | | | | | Vector compare using altivec 'vcmpxxx' instructions have as third argument a vector register instead of CR one, different from integer and float-point compares. This leads to a failure in code generation, where 'SelectSETCC' expects a DAG with a CR register and gets vector register instead. This patch changes the behavior by just returning a DAG with the vector compare instruction based on the type. The patch also adds a testcase for all vector types llvm defines. It also included a fix on signed 5-bits predicates printing, where signed values were not handled correctly as signed (char are unsigned by default for PowerPC). This generates 'vspltisw' (vector splat) instruction with SIM out of range. llvm-svn: 165419
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-271-1/+1
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-271-1/+1
| | | | llvm-svn: 164767
* Optimize zext on PPC64.Hal Finkel2012-08-281-0/+9
| | | | | | | | | | The zeroextend IR instruction is lowered to an 'and' node with an immediate mask operand, which in turn gets legalised to a sequence of ori's & ands. This can be done more efficiently using the rldicl instruction. Patch by Tobias von Koch. llvm-svn: 162724
* Treat TargetGlobalAddress as a constant for the purpose of matching pre-inc ↵Hal Finkel2012-06-211-1/+6
| | | | | | | | stores on PPC. Thanks to Tobias von Koch for pointing out this problem. llvm-svn: 158932
* Add support for generating reg+reg (indexed) pre-inc loads on PPC.Hal Finkel2012-06-201-2/+34
| | | | llvm-svn: 158823
* Add support for generating reg+reg preinc stores on PPC.Hal Finkel2012-06-191-0/+12
| | | | | | PPC will now generate STWUX and friends. llvm-svn: 158698
* Rename the PPC target feature gpul to mfocrf.Hal Finkel2012-06-111-2/+2
| | | | | | | | | | | The PPC target feature gpul (IsGigaProcessor) was only used for one thing: To enable the generation of the MFOCRF instruction. Furthermore, this instruction is available on other PPC cores outside of the G5 line. This feature now corresponds to the HasMFOCRF flag. No functionality change. llvm-svn: 158323
* Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-2/+2
| | | | | | since they are equivalent. llvm-svn: 155186
* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-041-2/+2
| | | | | | | | This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+0
| | | | llvm-svn: 148578
* MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR ↵Hal Finkel2011-12-081-1/+1
| | | | | | (another find by -verify-machineinstrs) llvm-svn: 146137
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-2/+2
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng2011-11-161-1/+0
| | | | | | | and code model. This eliminates the need to pass OptLevel flag all over the place and makes it possible for any codegen pass to use this information. llvm-svn: 144788
* Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to ↵Evan Cheng2011-07-261-1/+1
| | | | | | MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser. llvm-svn: 136027
* Don't apply on PPC64 the 32bit ADDIC optimizations as there's no overflowRoman Divacky2011-06-201-14/+23
| | | | | | with 32bit values. llvm-svn: 133439
* Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.Roman Divacky2011-06-031-1/+2
| | | | | | | | | | | | | - Check for MTCTR8 in addition to MTCTR when looking up a hazard. - When lowering an indirect call use CTR8 when targeting 64bit. - Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND. The last change fixes PR8487. With those changes, we are able to compile a running "ls" and "sh" on FreeBSD/PowerPC64. llvm-svn: 132552
* Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointlessCameron Zwarich2011-05-191-2/+2
| | | | | | | | piclabel operand. The operand in the tablegen definition doesn't actually turn into an MI operand, so it just confuses anything checking the TargetInstrDesc for the number of operands. It suffices to just have an implicit def of LR. llvm-svn: 131626
* Fix the last virtual register enumerations.Jakob Stoklund Olesen2011-01-081-3/+4
| | | | llvm-svn: 123102
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-241-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. llvm-svn: 122541
* whitespaceAndrew Trick2010-12-241-86/+86
| | | | llvm-svn: 122539
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-6/+6
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-8/+5
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* zap dead code.Chris Lattner2010-09-041-3/+0
| | | | llvm-svn: 113073
* The PPC MFCR instruction implicitly uses all 8 of the CRDale Johannesen2010-05-201-3/+5
| | | | | | | | | | | | | | registers. Currently it is not so marked, which leads to VCMPEQ instructions that feed into it getting deleted. If it is so marked, local RA complains about this sequence: vreg = MCRF CR0 MFCR <kill of whatever preg got assigned to vreg> All current uses of this instruction are only interested in one of the 8 CR registers, so redefine MFCR to be a normal unary instruction with a CR input (which is emitted only as a comment). That avoids all problems. 7739628. llvm-svn: 104238
* Use const qualifiers with TargetLowering. This eliminates severalDan Gohman2010-04-171-3/+2
| | | | | | | | | | | | | const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-2/+2
| | | | llvm-svn: 100214
* Make isInt?? and isUint?? template specializations of the generic versions. ThisBenjamin Kramer2010-03-291-10/+10
| | | | | | | makes calls a little bit more consistent and allows easy removal of the specializations in the future. Convert all callers to the templated functions. llvm-svn: 99838
* Sink InstructionSelect() out of each target into SDISel, and rename itChris Lattner2010-03-021-12/+0
| | | | | | | | | | | | DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader. Sink some other stuff out of DAGISelHeader into SDISel. Eliminate the various 'Indent' stuff from various targets, which dates to when isel was recursive. 17 files changed, 114 insertions(+), 430 deletions(-) llvm-svn: 97555
* Fix "the the" and similar typos.Dan Gohman2010-02-101-1/+1
| | | | llvm-svn: 95781
* Change SelectCode's argument from SDValue to SDNode *, to make it moreDan Gohman2010-01-051-19/+17
| | | | | | | | | clear what information these functions are actually using. This is also a micro-optimization, as passing a SDNode * around is simpler than passing a { SDNode *, int } by value or reference. llvm-svn: 92564
* Make capitalization of names starting "is" more consistent.Dale Johannesen2009-11-241-4/+4
| | | | | | No functional change. llvm-svn: 89724
* Remove an incorrect overaggressive optimizationDale Johannesen2009-11-201-5/+3
| | | | | | (PPC specific). llvm-svn: 89496
* Remove uninteresting and confusing debug output.Dan Gohman2009-11-051-2/+0
| | | | llvm-svn: 86149
* Remove includes of Support/Compiler.h that are no longer needed after theNick Lewycky2009-10-251-1/+0
| | | | | | VISIBILITY_HIDDEN removal. llvm-svn: 85043
* Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky2009-10-251-1/+1
| | | | | | | Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. llvm-svn: 85042
* Rename getTargetNode to getMachineNode, for consistency with theDan Gohman2009-09-251-80/+81
| | | | | | | | naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. llvm-svn: 82790
* Record variable debug info at ISel time directly.Devang Patel2009-08-221-41/+0
| | | | llvm-svn: 79742
* PowerPC inline asm was emitting two output operandsDale Johannesen2009-08-181-22/+6
| | | | | | | | | for a single "m" constraint; this is wrong because the opcode of a load or store would have to change in parallel. This patch makes it always compute addresses into a register, which is correct but not as efficient as possible. 7144566. llvm-svn: 79292
* Simplify a few more things, eliminating a few more dependencies onDan Gohman2009-08-151-1/+1
| | | | | | "the current basic block". llvm-svn: 79069
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-105/+105
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-104/+104
| | | | | | own struct type. llvm-svn: 78610
* Reapply r77654 with a fix: MachineFunctionPass's getAnalysisUsageDan Gohman2009-07-311-11/+6
| | | | | | | | shouldn't do AU.setPreservesCFG(), because even though CodeGen passes don't modify the LLVM IR CFG, they may modify the MachineFunction CFG, and passes like MachineLoop are registered with isCFGOnly set to true. llvm-svn: 77691
* Revert r77654, it appears to be causing llvm-gcc bootstrap failures, and manyDaniel Dunbar2009-07-311-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | failures when building assorted projects with clang. --- Reverse-merging r77654 into '.': U include/llvm/CodeGen/Passes.h U include/llvm/CodeGen/MachineFunctionPass.h U include/llvm/CodeGen/MachineFunction.h U include/llvm/CodeGen/LazyLiveness.h U include/llvm/CodeGen/SelectionDAGISel.h D include/llvm/CodeGen/MachineFunctionAnalysis.h U include/llvm/Function.h U lib/Target/CellSPU/SPUISelDAGToDAG.cpp U lib/Target/PowerPC/PPCISelDAGToDAG.cpp U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/MachineVerifier.cpp U lib/CodeGen/MachineFunction.cpp U lib/CodeGen/PrologEpilogInserter.cpp U lib/CodeGen/MachineLoopInfo.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp D lib/CodeGen/MachineFunctionAnalysis.cpp D lib/CodeGen/MachineFunctionPass.cpp U lib/CodeGen/LiveVariables.cpp llvm-svn: 77661
* Manage MachineFunctions with an analysis Pass instead of the AnnotableDan Gohman2009-07-311-11/+6
| | | | | | | mechanism. To support this, make MachineFunctionPass a little more complete. llvm-svn: 77654
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-7/+7
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-4/+4
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Implement changes from Chris's feedback.Torok Edwin2009-07-081-3/+5
| | | | | | Finish converting lib/Target. llvm-svn: 75043
* Fix some failures in targets on available_externally functions,Chris Lattner2009-04-171-0/+6
| | | | | | | this fixes a crash on CodeGen/Generic/externally_available.ll on ppc hosts. Thanks to Nicholas L for pointing this out. llvm-svn: 69333
* Remove refs to non-DebugLoc version of BuildMI from PowerPC.Dale Johannesen2009-02-131-8/+10
| | | | llvm-svn: 64431
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