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path: root/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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* Make FP tests requiring two compares work on PPC (PR 642).Dale Johannesen2008-11-071-16/+19
* Reintroduce a comment that was removed with the AddToISelQueueDan Gohman2008-11-051-0/+1
* Eliminate the ISel priority queue, which used the topological order for aDan Gohman2008-11-051-27/+1
* Have TableGen emit setSubgraphColor calls under control of a -gen-debugDavid Greene2008-10-271-1/+1
* Trim #includes.Dan Gohman2008-10-161-2/+0
* Avoid creating two TargetLowering objects for each target.Dan Gohman2008-10-031-2/+2
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-8/+8
* Clean up uses of TargetLowering::getTargetMachine.Dan Gohman2008-09-041-1/+1
* fix a bunch of 80-col violationsGabor Greif2008-08-311-2/+4
* erect abstraction boundaries for accessing SDValue members, rename Val -> Nod...Gabor Greif2008-08-281-12/+12
* Move the point at which FastISel taps into the SelectionDAGISelDan Gohman2008-08-231-5/+4
* Simplify SelectRoot's interface, and factor out some common codeDan Gohman2008-08-211-1/+1
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-108/+108
* Add a new function, ReplaceAllUsesOfValuesWith, which handles bulkDan Gohman2008-07-171-3/+3
* Add explicit keywords.Dan Gohman2008-07-071-1/+1
* Split scheduling from instruction selection.Evan Cheng2008-06-301-7/+4
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-3/+3
* Convert the last remaining users of the non-APInt form ofDan Gohman2008-02-271-5/+5
* Remove bunch of gcc 4.3-related warnings from TargetAnton Korobeynikov2008-02-201-2/+2
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+1
* Dwarf requires variable entries to be in the source order. Right now, since w...Evan Cheng2008-02-041-1/+0
* SDIsel processes llvm.dbg.declare by recording the variable debug information...Evan Cheng2008-02-021-0/+1
* Factor the addressing mode and the load/store VT out of LoadSDNodeDan Gohman2008-01-301-1/+1
* Finally implement correct ordered comparisons for PPC, even thoughChris Lattner2008-01-081-24/+43
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-2/+2
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-1/+1
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-071-2/+3
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-9/+7
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
* Temporary solution: added a different set of BCTRL_Macho / BCTRL_ELF with rig...Evan Cheng2007-10-231-3/+5
* Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI ...Evan Cheng2007-06-291-1/+4
* Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits fromDan Gohman2007-06-221-2/+2
* Fix a bug which caused us to never be able to use signed comparisons forChris Lattner2007-04-021-1/+1
* eliminate static ctors for Statistic objects.Chris Lattner2006-12-191-3/+1
* Reduce number of instructions to load 64-bit constants.Jim Laskey2006-12-121-0/+75
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-1/+0
* Detemplatize the Statistic class. The only type it is instantiated withChris Lattner2006-12-061-1/+1
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-9/+10
* convert PPC::BCC to use the 'pred' operand instead of separate predicateChris Lattner2006-11-171-1/+11
* rename PPC::COND_BRANCH to PPC::BCCChris Lattner2006-11-171-1/+1
* start using PPC predicates more consistently.Chris Lattner2006-11-171-14/+12
* add patterns for ppc32 preinc stores. ppc64 next.Chris Lattner2006-11-161-0/+8
* fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memriChris Lattner2006-11-151-27/+28
* remove a ton of custom selection logic no longer neededChris Lattner2006-11-141-145/+7
* allow the offset of a preinc'd load to be the low-part of a global. ThisChris Lattner2006-11-111-1/+2
* implement preinc support for r+i loads on ppc64Chris Lattner2006-11-101-8/+23
* add an initial cut at preinc loads for ppc32. This is broken for ppc64Chris Lattner2006-11-101-0/+38
* Match tblegen changes.Evan Cheng2006-11-081-9/+12
* Refactor all the addressing mode selection stuff into the isel loweringChris Lattner2006-11-081-228/+13
* For PR786:Reid Spencer2006-11-021-2/+0
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