| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
| |
Although I had added some support for the BDZ/BDNZ branches into the selector
(in r158204), I had not correctly adjusted the condition at the top of the
loop. As a result, these branches were still essentially unsupported.
This fixes PR16086. Unfortunately, any test case would be very large (because
it would need to force the loop backedge to exceed the range of the 16-bit
immediate).
llvm-svn: 182385
|
|
|
|
|
|
| |
via -print-after-all.
llvm-svn: 175058
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
llvm-svn: 169131
|
|
|
|
|
|
|
|
|
|
| |
CTR-based loop branching code.
This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon
pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are
no longer otherwise used. Also, invalid preheader DebugLoc is not used.
llvm-svn: 158204
|
|
|
|
|
|
| |
MSP430, PPC, PTX, Sparc, X86, XCore.
llvm-svn: 150878
|
|
|
|
|
|
| |
MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
llvm-svn: 136027
|
|
|
|
| |
llvm-svn: 111835
|
|
|
|
| |
llvm-svn: 110460
|
|
|
|
| |
llvm-svn: 110410
|
|
|
|
|
|
|
|
| |
address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.
llvm-svn: 110396
|
|
|
|
| |
llvm-svn: 109224
|
|
|
|
|
|
|
|
| |
ARM/PPC/MSP430-specific code (which are the only targets that
implement the hook) can directly reference their target-specific
instrinfo classes.
llvm-svn: 109171
|
|
|
|
|
|
|
| |
makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.
llvm-svn: 99838
|
|
|
|
|
|
| |
VISIBILITY_HIDDEN removal.
llvm-svn: 85043
|
|
|
|
|
|
|
| |
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
llvm-svn: 85042
|
|
|
|
| |
llvm-svn: 64431
|
|
|
|
|
|
| |
isReg, etc., from isRegister, etc.
llvm-svn: 57006
|
|
|
|
| |
llvm-svn: 55779
|
|
|
|
|
|
| |
instruction. X86, PowerPC and ARM are implemented
llvm-svn: 49809
|
|
|
|
|
|
| |
independent one: TargetInstrInfo::IMPLICIT_DEF.
llvm-svn: 48380
|
|
|
|
|
|
|
|
|
|
|
|
| |
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
llvm-svn: 45464
|
|
|
|
| |
llvm-svn: 45418
|
|
|
|
|
|
|
| |
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
llvm-svn: 41958
|
|
|
|
| |
llvm-svn: 36662
|
|
|
|
|
|
|
| |
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
llvm-svn: 36652
|
|
|
|
| |
llvm-svn: 36632
|
|
|
|
| |
llvm-svn: 33537
|
|
|
|
| |
llvm-svn: 32703
|
|
|
|
|
|
| |
is 'unsigned'.
llvm-svn: 32279
|
|
|
|
|
|
| |
of opcode and number of operands.
llvm-svn: 31947
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The algorithm it used before wasn't 100% correct, we now use an iterative
expansion model. This fixes assembler errors when compiling 403.gcc with
tail merging enabled.
Change the way the branch selector works overall: Now, the isel generates
PPC::BCC instructions (as it used to) directly, and these BCC instructions
are emitted to the output or jitted directly if branches don't need
expansion. Only if branches need expansion are instructions rewritten
and created. This should make branch select faster, and eliminates the
Bxx instructions from the .td file.
llvm-svn: 31837
|
|
|
|
|
|
|
|
| |
value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(
llvm-svn: 31835
|
|
|
|
| |
llvm-svn: 31834
|
|
|
|
| |
llvm-svn: 31833
|
|
|
|
| |
llvm-svn: 31823
|
|
|
|
| |
llvm-svn: 31805
|
|
|
|
| |
llvm-svn: 31799
|
|
|
|
| |
llvm-svn: 31797
|
|
|
|
| |
llvm-svn: 31785
|
|
|
|
| |
llvm-svn: 30935
|
|
|
|
| |
llvm-svn: 29911
|
|
|
|
| |
llvm-svn: 29889
|
|
|
|
|
|
|
|
|
| |
asm printer will print it as offset*4. e.g. bne cr0, $+8.
The PPC code emitter was expecting the offset to be number of instructions, not
number of bytes. This fixes a whole bunch of JIT failures.
llvm-svn: 29885
|
|
|
|
|
|
| |
dropped. This shrinks libllvmgcc.dylib another 67K
llvm-svn: 28975
|
|
|
|
| |
llvm-svn: 28929
|
|
|
|
| |
llvm-svn: 28099
|
|
|
|
|
|
|
|
| |
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
llvm-svn: 26814
|
|
|
|
|
|
|
|
| |
Move the methods out of line.
Remove unused Debug.h stuff.
Teach getNumBytesForInstruction to know the size of an inline asm.
llvm-svn: 26064
|
|
|
|
|
|
| |
redundant after the change.
llvm-svn: 23759
|
|
|
|
|
|
| |
This completes the grand PPC file renaming
llvm-svn: 23745
|