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path: root/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
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* teach getClass what a condition reg isChris Lattner2005-08-261-3/+5
* Minor cleanups:Chris Lattner2005-08-261-7/+8
* Now that the simple isels are dead, so is this.Chris Lattner2005-08-191-20/+0
* MFLR doesn't take an operand, the LR register is implicitChris Lattner2005-08-181-1/+1
* Use the new subtarget support to automatically choose the correct ABINate Begeman2005-08-041-5/+0
* Keep tabs and trailing spaces out.Jeff Cohen2005-07-301-1/+1
* Fix some commentsNate Begeman2005-07-271-1/+1
* Implement the optimization for the Red Zone on Darwin. This removes theNate Begeman2005-07-271-3/+8
* Convert tabs to spacesMisha Brukman2005-04-221-1/+1
* Remove trailing whitespaceMisha Brukman2005-04-211-18/+18
* Initial support for allocation condition registersNate Begeman2005-04-121-1/+14
* Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do notNate Begeman2005-04-101-4/+0
* Remove unnecessary register copy now that regalloc is fixedNate Begeman2005-04-041-2/+0
* Eliminate usage of MRegisterInfo::getRegClass(physreg)Nate Begeman2004-10-261-5/+9
* Correct some BuildMI arguments for the upcoming simple schedulerNate Begeman2004-09-271-1/+1
* Changes For Bug 352Reid Spencer2004-09-011-3/+3
* Register sizes are in bits, not bytesNate Begeman2004-08-271-2/+2
* Don't hard code the offset of the saved R31 in functions with frame pointersNate Begeman2004-08-221-1/+2
* Reduce uses of getRegClassChris Lattner2004-08-211-4/+3
* PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC*Misha Brukman2004-08-171-0/+316
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