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* Adjust to changes in Makefile.rulesReid Spencer2004-10-221-1/+1
| | | | llvm-svn: 17167
* Don't clear or sign extend bool->int. This fires a few dozen times on the ↵Nate Begeman2004-10-201-0/+17
| | | | | | test suite llvm-svn: 17147
* Implement bitfield insert by recognizing the following pattern:Nate Begeman2004-10-171-5/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. optional shift left 2. and x, immX 3. and y, immY 4. or z, x, y ==> rlwimi z, x, y, shift, mask begin, mask end where immX == ~immY and immX is a run of set bits. This transformation fires 32 times on voronoi, once on espresso, and probably several dozen times on external benchmarks such as gcc. To put this in terms of actual code generated for struct B { unsigned a : 3; unsigned b : 2; }; void storeA (struct B *b, int v) { b->a = v;} void storeB (struct B *b, int v) { b->b = v;} Old: _storeA: rlwinm r2, r4, 0, 29, 31 lwz r4, 0(r3) rlwinm r4, r4, 0, 0, 28 or r2, r4, r2 stw r2, 0(r3) blr _storeB: rlwinm r2, r4, 3, 0, 28 rlwinm r2, r2, 0, 27, 28 lwz r4, 0(r3) rlwinm r4, r4, 0, 29, 26 or r2, r2, r4 stw r2, 0(r3) blr New: _storeA: lwz r2, 0(r3) rlwimi r2, r4, 0, 29, 31 stw r2, 0(r3) blr _storeB: lwz r2, 0(r3) rlwimi r2, r4, 3, 27, 28 stw r2, 0(r3) blr llvm-svn: 17078
* Finally fix one of the oldest FIXMEs in the PowerPC backend: correctlyNate Begeman2004-10-161-10/+8
| | | | | | | | | | flag rotate left word immediate then mask insert (rlwimi) as a two-address instruction, and update the ISel usage of the instruction accordingly. This will allow us to properly schedule rlwimi, and use it to efficiently codegen bitfield operations. llvm-svn: 17068
* ADd support for undef and unreachableChris Lattner2004-10-161-4/+8
| | | | llvm-svn: 17050
* Better codegen of binary integer ops with 32 bit immediate operands.Nate Begeman2004-10-151-2/+22
| | | | | | | | | | | | | | | | | | | | This transformation fires a few dozen times across the testsuite. For example, int test2(int X) { return X ^ 0x0FF00FF0; } Old: _test2: lis r2, 4080 ori r2, r2, 4080 xor r3, r3, r2 blr New: _test2: xoris r3, r3, 4080 xori r3, r3, 4080 blr llvm-svn: 17004
* Implement logical and with an immediate that consists of a contiguous blockNate Begeman2004-10-081-5/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of one or more 1 bits (may wrap from least significant bit to most significant bit) as the rlwinm rather than andi., andis., or some longer instructons sequence. int andn4(int z) { return z & -4; } int clearhi(int z) { return z & 0x0000FFFF; } int clearlo(int z) { return z & 0xFFFF0000; } int clearmid(int z) { return z & 0x00FFFF00; } int clearwrap(int z) { return z & 0xFF0000FF; } _andn4: rlwinm r3, r3, 0, 0, 29 blr _clearhi: rlwinm r3, r3, 0, 16, 31 blr _clearlo: rlwinm r3, r3, 0, 0, 15 blr _clearmid: rlwinm r3, r3, 0, 8, 23 blr _clearwrap: rlwinm r3, r3, 0, 24, 7 blr llvm-svn: 16832
* Several fixes and enhancements to the PPC32 backend.Nate Begeman2004-10-071-143/+127
| | | | | | | | | | | | | | | | | | | | | | 1. Fix an illegal argument to getClassB when deciding whether or not to sign extend a byte load. 2. Initial addition of isLoad and isStore flags to the instruction .td file for eventual use in a scheduler. 3. Rewrite of how constants are handled in emitSimpleBinaryOperation so that we can emit the PowerPC shifted immediate instructions far more often. This allows us to emit the following code: int foo(int x) { return x | 0x00F0000; } _foo: .LBB_foo_0: ; entry ; IMPLICIT_DEF oris r3, r3, 15 blr llvm-svn: 16826
* Correct some typeosChris Lattner2004-10-061-3/+3
| | | | llvm-svn: 16770
* Turning on fsel code gen now that we can do so would be good.Nate Begeman2004-10-061-11/+10
| | | | llvm-svn: 16765
* Implement floating point select for lt, gt, le, ge using the powerpc fselNate Begeman2004-10-061-25/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instruction. Now, rather than emitting the following loop out of bisect: .LBB_main_19: ; no_exit.0.i rlwinm r3, r2, 3, 0, 28 lfdx f1, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f2, f2, f1 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3) fcmpu cr0, f1, f4 bge .LBB_main_64 ; no_exit.0.i .LBB_main_63: ; no_exit.0.i b .LBB_main_65 ; no_exit.0.i .LBB_main_64: ; no_exit.0.i fmr f2, f1 .LBB_main_65: ; no_exit.0.i addi r3, r2, 1 rlwinm r3, r3, 3, 0, 28 lfdx f1, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f4, f4, f1 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f5, lo16(.CPI_main_1-"L00000$pb")(r3) fcmpu cr0, f1, f5 bge .LBB_main_67 ; no_exit.0.i .LBB_main_66: ; no_exit.0.i b .LBB_main_68 ; no_exit.0.i .LBB_main_67: ; no_exit.0.i fmr f4, f1 .LBB_main_68: ; no_exit.0.i fadd f1, f2, f4 addis r3, r30, ha16(.CPI_main_2-"L00000$pb") lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3) fmul f1, f1, f2 rlwinm r3, r2, 3, 0, 28 lfdx f2, r3, r28 fadd f4, f2, f1 fcmpu cr0, f4, f0 bgt .LBB_main_70 ; no_exit.0.i .LBB_main_69: ; no_exit.0.i b .LBB_main_71 ; no_exit.0.i .LBB_main_70: ; no_exit.0.i fmr f0, f4 .LBB_main_71: ; no_exit.0.i fsub f1, f2, f1 addi r2, r2, -1 fcmpu cr0, f1, f3 blt .LBB_main_73 ; no_exit.0.i .LBB_main_72: ; no_exit.0.i b .LBB_main_74 ; no_exit.0.i .LBB_main_73: ; no_exit.0.i fmr f3, f1 .LBB_main_74: ; no_exit.0.i cmpwi cr0, r2, -1 fmr f16, f0 fmr f17, f3 bgt .LBB_main_19 ; no_exit.0.i We emit this instead: .LBB_main_19: ; no_exit.0.i rlwinm r3, r2, 3, 0, 28 lfdx f1, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f2, f2, f1 fsel f1, f1, f1, f2 addi r3, r2, 1 rlwinm r3, r3, 3, 0, 28 lfdx f2, r3, r27 addis r3, r30, ha16(.CPI_main_1-"L00000$pb") lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3) fsub f4, f4, f2 fsel f2, f2, f2, f4 fadd f1, f1, f2 addis r3, r30, ha16(.CPI_main_2-"L00000$pb") lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3) fmul f1, f1, f2 rlwinm r3, r2, 3, 0, 28 lfdx f2, r3, r28 fadd f4, f2, f1 fsub f5, f0, f4 fsel f0, f5, f0, f4 fsub f1, f2, f1 addi r2, r2, -1 fsub f2, f1, f3 fsel f3, f2, f3, f1 cmpwi cr0, r2, -1 fmr f16, f0 fmr f17, f3 bgt .LBB_main_19 ; no_exit.0.i llvm-svn: 16764
* Generate better code by being far less clever when it comes to the select ↵Nate Begeman2004-09-291-7/+17
| | | | | | instruction. Don't create overlapping register lifetimes llvm-svn: 16580
* improve Type::BoolTy codegen by eliminating unnecessary clears and sign extendsNate Begeman2004-09-291-1/+8
| | | | llvm-svn: 16578
* To go along with sabre's improved InstCombining, improve recognition ofNate Begeman2004-09-291-21/+9
| | | | | | | | | | | | | | | integers that we can use as immediate values in instructions. Example from yacr2: - lis r10, -1 - ori r10, r10, 65535 - add r28, r28, r10 + addi r28, r28, -1 addi r7, r7, 1 addi r9, r9, 1 b .LBB_main_9 ; loopentry.1.i214 llvm-svn: 16566
* Correct some BuildMI arguments for the upcoming simple schedulerNate Begeman2004-09-271-1/+1
| | | | llvm-svn: 16519
* Fix the last of the major PPC GEP folding deficiencies. This will allowNate Begeman2004-09-231-178/+163
| | | | | | | | the ISel to use indexed and non-zero immediate offsets for GEPs that have more than one use. This is common for instruction sequences such as a load followed by a modify and store to the same address. llvm-svn: 16493
* add optimized code sequences for setcc x, 0Nate Begeman2004-09-221-5/+92
| | | | llvm-svn: 16478
* s/ISel/PPC32ISel/ to have unique class names for debugging via gdb because theMisha Brukman2004-09-211-87/+90
| | | | | | C++ front-end in gcc does not mangle classes in anonymous namespaces correctly. llvm-svn: 16470
* All PPC instructions are now auto-printedNate Begeman2004-09-041-3/+4
| | | | | | | 32 and 64 bit AsmWriters unified Darwin and AIX specific features of AsmWriter split out llvm-svn: 16163
* Convert remaining X-Form and Pseudo instructions over to asm writerNate Begeman2004-09-021-2/+2
| | | | llvm-svn: 16142
* Changes For Bug 352Reid Spencer2004-09-011-2/+2
| | | | | | | | Move include/Config and include/Support into include/llvm/Config, include/llvm/ADT and include/llvm/Support. From here on out, all LLVM public header files must be under include/llvm/. llvm-svn: 16137
* Implement the following missing functionality in the PPC backend:Nate Begeman2004-08-291-44/+135
| | | | | | | | | cast fp->bool cast ulong->fp algebraic right shift long by non-constant value These changes tested across most of the test suite. Fixes Regression/casts llvm-svn: 16081
* Kill a majority of unnecessary sign extensions for byte loadsNate Begeman2004-08-221-12/+30
| | | | llvm-svn: 15991
* Back out branchless SetCC code. While it helped a lot in some cases, itNate Begeman2004-08-211-188/+25
| | | | | | | | hurt a lot in others. Instead, improve branching version of SetCC and Select instructions. The old code will be in CVS should we ever need to dig it up again. llvm-svn: 15979
* Implement code to convert SetCC into straight line code where appropriate. ↵Nate Begeman2004-08-201-22/+169
| | | | | | Add necessary instructions for this transformation to the .td file. llvm-svn: 15952
* This PHI has 4 additional operands, not 2.Misha Brukman2004-08-191-1/+1
| | | | llvm-svn: 15926
* Convert casts that will have no effect into move instructions.Nate Begeman2004-08-191-4/+22
| | | | llvm-svn: 15914
* Clean up floating point instruction selection.Nate Begeman2004-08-191-53/+10
| | | | | | | | Change int->float cast code to put conversion constants in constant pool. Shorten code sequence for constant pool fp loads. Remove LOADLoDirect/LOADLoIndirect psuedo instructions and tweak asmwriter llvm-svn: 15913
* Re-fix hiding the Frame Pointer from the register allocator in functionsNate Begeman2004-08-171-19/+7
| | | | | | | | that have a frame pointer. This change fixes Burg. In addition, make the necessary changes to floating point code gen and constant loading after Chris Lattner's fixes to the asm writer. These changes fix MallocBench/gs llvm-svn: 15873
* PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC*Misha Brukman2004-08-171-6/+6
| | | | llvm-svn: 15850
* Fix mismatched adjust down/up of SP in functions that contain variableNate Begeman2004-08-161-4/+4
| | | | | | sized allocas. llvm-svn: 15806
* Fix float to int codepath by always allocating 8 bytes for the target of a ↵Nate Begeman2004-08-151-6/+9
| | | | | | double store; optimize cmplwi generation. llvm-svn: 15759
* Fix handling of FP constants with single precision, and loading of internal ↵Nate Begeman2004-08-141-27/+27
| | | | | | linkage function addresses llvm-svn: 15742
* Fix siod by switching BoolTy to byte rather than int until CFE changes forNate Begeman2004-08-131-1/+1
| | | | | | | Darwin. Also, change asm printer to output proper stubs for external functions whose address is passed as an argument to aid in bugpointing. llvm-svn: 15721
* Fix 177.mesa compilation, don't use floating point regs for base addresses!Nate Begeman2004-08-131-1/+1
| | | | llvm-svn: 15720
* Fix llc crasher compiling siod by giving BuildMI the correct number of argumentsNate Begeman2004-08-131-1/+1
| | | | llvm-svn: 15719
* Clean up 32/64bit and Darwin/AIX split. Next steps: 64 bit ISel, AIX asm ↵Nate Begeman2004-08-111-1/+0
| | | | | | printer. llvm-svn: 15662
* Fix a case where constantexprs could leak into the PPC isel.Chris Lattner2004-08-111-1/+4
| | | | llvm-svn: 15661
* Fix 255.vortex by using getClassB instead of getClassNate Begeman2004-08-111-2/+1
| | | | llvm-svn: 15648
* Breaking up the PowerPC target into 32- and 64-bit subparts, Part I: 32-bit.Misha Brukman2004-08-111-7/+7
| | | | llvm-svn: 15634
* Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targetsMisha Brukman2004-08-101-372/+372
| | | | llvm-svn: 15631
* Fix casts of float to unsigned longNate Begeman2004-08-101-28/+84
| | | | | | | | Replace STDX (store 64 bit int indexed) with STFDX (store double indexed) Fix latent bug in indexed load generation Generate indexed loads and stores in many more cases llvm-svn: 15626
* Changes commited for Nate Begeman:Chris Lattner2004-08-061-12/+17
| | | | | | | | | | | | | | | Use a PowerPC specific prolog epilog inserter to control where spilled callee save regs are placed on the stack. Get rid of implicit return address stack slot, save return address reg (LR) in appropriate slot Improve code generated for functions that don't have calls or access globals Note from Chris: PowerPCPEI will eventually be eliminated, once the functionality is merged into CodeGen/PrologEpilogInserter.cpp llvm-svn: 15536
* Simplify loading (un)signed constants to registers, patch by Nate Begeman.Misha Brukman2004-07-281-45/+47
| | | | llvm-svn: 15306
* LI can only take signed values, so values > 32767 can only be loaded with ORIMisha Brukman2004-07-281-1/+7
| | | | llvm-svn: 15299
* Build COND_BRANCHes which may become long or short, decided by a later pass.Misha Brukman2004-07-271-23/+14
| | | | | | Patch by Nate Begeman. llvm-svn: 15282
* Add IMPLICIT_DEF of LR for branch-and-link instrs (calls and global accesses)Misha Brukman2004-07-271-0/+2
| | | | llvm-svn: 15270
* * Rewrote castsMisha Brukman2004-07-261-192/+510
| | | | | | | | | | * Implemented GEP folding * Dynamically output global address stuff once per function * Fix casting fp<->short/byte Patch contributed by Nate Begeman. llvm-svn: 15237
* Eliminate spurious empty space; make code easier to page through.Misha Brukman2004-07-231-21/+12
| | | | llvm-svn: 15146
* Implement casting a floating point to 32-bit unsigned valueMisha Brukman2004-07-231-2/+61
| | | | llvm-svn: 15143
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