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path: root/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
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* Fix PowerPC varargsChris Lattner2005-07-051-24/+25
| | | | llvm-svn: 22335
* Varargs is apparently currently broken on PPC. This hacks it so that itChris Lattner2005-07-011-4/+9
| | | | | | | | is at least overloading the right virtual methods. The implementations are currently wrong though. This fixes Ptrdist/bc, but not other programs (e.g. siod). llvm-svn: 22326
* Commit fix for generating conditional branch pseudo instructions thatNate Begeman2005-06-151-3/+8
| | | | | | | avoids dereferencing the end() iterator when selecting the fallthrough block. This requires an ilist change. llvm-svn: 22212
* Commit a small improvement that is already in the x86 and ia64 backends toNate Begeman2005-06-141-0/+5
| | | | | | | not generate unnecessary register copies. This improves compile time by 2-5% depending on the test. llvm-svn: 22210
* Handle some more real world cases of rlwimi. These don't come up thatNate Begeman2005-06-081-10/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | regularly in "normal" code, but for things like software graphics, they make a big difference. For the following code: unsigned short Trans16Bit(unsigned srcA,unsigned srcB,unsigned alpha) { unsigned tmpA,tmpB,mixed; tmpA = ((srcA & 0x03E0) << 15) | (srcA & 0x7C1F); tmpB = ((srcB & 0x03E0) << 15) | (srcB & 0x7C1F); mixed = (tmpA * alpha) + (tmpB * (32 - alpha)); return ((mixed >> 5) & 0x7C1F) | ((mixed >> 20) & 0x03E0); } We now generate: _Trans16Bit: .LBB_Trans16Bit_0: ; entry andi. r2, r4, 31775 rlwimi r2, r4, 15, 7, 11 subfic r4, r5, 32 mullw r2, r2, r4 andi. r4, r3, 31775 rlwimi r4, r3, 15, 7, 11 mullw r3, r4, r5 add r2, r2, r3 srwi r3, r2, 5 andi. r3, r3, 31775 rlwimi r3, r2, 12, 22, 26 blr Instead of: _Trans16Bit: .LBB_Trans16Bit_0: ; entry slwi r2, r4, 15 rlwinm r2, r2, 0, 7, 11 andi. r4, r4, 31775 or r2, r2, r4 subfic r4, r5, 32 mullw r2, r2, r4 slwi r4, r3, 15 rlwinm r4, r4, 0, 7, 11 andi. r3, r3, 31775 or r3, r4, r3 mullw r3, r3, r5 add r2, r2, r3 srwi r3, r2, 5 andi. r3, r3, 31775 srwi r2, r2, 20 rlwimi r3, r2, 0, 22, 26 blr llvm-svn: 22201
* Fix andrews changes to fit in 80 columnsChris Lattner2005-05-151-9/+18
| | | | llvm-svn: 22064
* treat TAILCALL nodes identically to CALL nodesChris Lattner2005-05-131-1/+4
| | | | llvm-svn: 21977
* Add an isTailCall flag to LowerCallToChris Lattner2005-05-131-2/+3
| | | | llvm-svn: 21958
* Realize that we don't support fmod directly, fixing ↵Chris Lattner2005-05-131-1/+3
| | | | | | CodeGen/Generic/print-arith-fp.ll llvm-svn: 21939
* rename the ADJCALLSTACKDOWN/ADJCALLSTACKUP nodes to be CALLSEQ_START/BEGIN.Chris Lattner2005-05-121-6/+6
| | | | llvm-svn: 21915
* Pass in Calling Convention to use into LowerCallToChris Lattner2005-05-121-1/+2
| | | | llvm-svn: 21899
* These targets don't like setccChris Lattner2005-05-121-0/+3
| | | | llvm-svn: 21884
* Necessary changes to codegen cttz efficiently on PowerPCNate Begeman2005-05-111-6/+28
| | | | | | | | | | 1. Teach LegalizeDAG how to better legalize CTTZ if the target doesn't have CTPOP, but does have CTLZ 2. Teach PPC32 how to do sub x, const -> add x, -const for valid consts 3. Teach PPC32 how to do and (xor a, -1) b -> andc b, a 4. Teach PPC32 that ISD::CTLZ -> PPC::CNTLZW llvm-svn: 21880
* fold and (shl X, C1), C2 -> rlwinm when possible. Many other cases are ↵Chris Lattner2005-05-091-1/+20
| | | | | | | | possible, include and (srl) and the inverses (shl and) etc. llvm-svn: 21820
* fix typoAndrew Lenharth2005-05-041-1/+1
| | | | llvm-svn: 21693
* Implement count leading zeros (ctlz), count trailing zeros (cttz), and countAndrew Lenharth2005-05-031-0/+5
| | | | | | | | | population (ctpop). Generic lowering is implemented, however only promotion is implemented for SelectionDAG at the moment. More coming soon. llvm-svn: 21676
* This target doesn't support the FSIN/FCOS/FSQRT nodes yetChris Lattner2005-04-301-0/+8
| | | | llvm-svn: 21633
* Implement Value* tracking for loads and stores in the selection DAG. This ↵Andrew Lenharth2005-04-271-11/+11
| | | | | | | | enables one to use alias analysis in the backends. (TRUNK)Stores and (EXT|ZEXT|SEXT)Loads have an extra SDOperand which is a SrcValueSDNode which contains the Value*. Note that if the operation is introduced by the backend, it will still have the operand, but the value* will be null. llvm-svn: 21599
* Convert tabs to spacesMisha Brukman2005-04-221-3/+4
| | | | llvm-svn: 21452
* Remove trailing whitespaceMisha Brukman2005-04-211-135/+135
| | | | llvm-svn: 21425
* Match another form of eqvChris Lattner2005-04-211-1/+6
| | | | llvm-svn: 21413
* Next round of PPC CR optimizations. For the following code:Nate Begeman2005-04-181-62/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | int %bar(float %a, float %b, float %c, float %d) { entry: %tmp.1 = setlt float %a, %d %tmp.2 = setlt float %b, %d %or = or bool %tmp.1, %tmp.2 %tmp.3 = setgt float %c, %d %tmp.4 = or bool %or, %tmp.3 %tmp.5 = and bool %tmp.4, true %retval = cast bool %tmp.5 to int ret int %retval } We now emit: _bar: .LBB_bar_0: ; entry fcmpu cr0, f1, f4 fcmpu cr1, f2, f4 cror 0, 0, 4 fcmpu cr1, f3, f4 cror 28, 0, 5 mfcr r2 rlwinm r3, r2, 29, 31, 31 blr Instead of: _bar: .LBB_bar_0: ; entry fcmpu cr7, f1, f4 mfcr r2 rlwinm r2, r2, 29, 31, 31 fcmpu cr7, f2, f4 mfcr r3 rlwinm r3, r3, 29, 31, 31 or r2, r2, r3 fcmpu cr7, f3, f4 mfcr r3 rlwinm r3, r3, 30, 31, 31 or r3, r2, r3 blr llvm-svn: 21321
* Change codegen for setcc to read the bit directly out of the conditionNate Begeman2005-04-181-42/+31
| | | | | | | | register. Added support in the .td file for the g5-specific variant of cr -> gpr moves that executes faster, but we currently don't generate it. llvm-svn: 21314
* Make pattern isel default for ppcNate Begeman2005-04-151-3/+2
| | | | | | | | | | Add new ppc beta option related to using condition registers Make pattern isel control flag (-enable-pattern-isel) global and tristate 0 == off 1 == on 2 == target default llvm-svn: 21309
* Implement multi-way branches through logical ops on condition registers.Nate Begeman2005-04-141-2/+68
| | | | | | | | This can generate considerably shorter code, reducing the size of crafty by almost 1%. Also fix the printing of mcrf. The code is currently disabled until it gets a bit more testing, but should work as-is. llvm-svn: 21298
* Start allocating condition registers. Almost all explicit uses of CR0 areNate Begeman2005-04-131-23/+26
| | | | | | | now gone. Next step is to get rid of the remaining ones and then start allocating bools to CRs where appropriate. llvm-svn: 21294
* Implement the fold shift X, zext(Y) -> shift X, Y at the target level,Nate Begeman2005-04-131-6/+22
| | | | | | where it is safe to do so. llvm-svn: 21293
* Disbale the broken fold of shift + sz[ext] for nowNate Begeman2005-04-131-19/+0
| | | | | | | | Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc always produces zero or one. llvm-svn: 21291
* remove one more occurance of this that snuck inChris Lattner2005-04-131-1/+1
| | | | llvm-svn: 21271
* Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emitChris Lattner2005-04-131-13/+0
| | | | | | | andi instructions instead of rlwinm instructions for zero extend, but they seem like they would take the same time. llvm-svn: 21268
* Fold shift by size larger than type size to undefNate Begeman2005-04-121-1/+0
| | | | | | Make llvm undef values generate ISD::UNDEF nodes llvm-svn: 21261
* Implement setcc op, -1 sequencesNate Begeman2005-04-121-22/+41
| | | | | | | Remove dead setcc op, 0 sequences Coming later: generalization of op, imm llvm-svn: 21260
* Implement bitfield clearsNate Begeman2005-04-121-11/+31
| | | | | | Implement divide by negative power of two llvm-svn: 21240
* Add recording variants of ISD::AND and ISD::OR. This kills almost 1000Nate Begeman2005-04-111-10/+43
| | | | | | (1.5%) instructions in 186.crafty llvm-svn: 21222
* Fix another fixme: factor out the constant fp generation code.Nate Begeman2005-04-101-17/+2
| | | | llvm-svn: 21207
* Fix 64 bit argument loading that straddles the args in regs / args on stackNate Begeman2005-04-101-7/+15
| | | | | | boundary. llvm-svn: 21206
* Make sure that BRCOND branches can be converted into long branches too.Nate Begeman2005-04-101-1/+3
| | | | llvm-svn: 21198
* Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.Nate Begeman2005-04-101-1/+2
| | | | llvm-svn: 21197
* fix ISD::BRCONDTWOWAY codegen to not deference the end() iteratorNate Begeman2005-04-091-1/+1
| | | | llvm-svn: 21193
* do not set the root to null if an argument is deadChris Lattner2005-04-091-1/+2
| | | | llvm-svn: 21188
* Add rlwnm instruction for variable rotateNate Begeman2005-04-091-28/+76
| | | | | | | | Generate rotate left/right immediate Generate code for brcondtwoway Use new livein/liveout functionality llvm-svn: 21187
* Optimize FSEL a bit for fneg arguments. This fixes the recently added testNate Begeman2005-04-091-11/+12
| | | | | | | | | | | | | | | | | | | | case so that we emit _test_fneg_sel: .LBB_test_fneg_sel_0: ; fsel f1, f1, f3, f2 blr instead of: _test_fneg_sel: .LBB_test_fneg_sel_0: ; fneg f0, f1 fneg f0, f0 fsel f1, f0, f3, f2 blr llvm-svn: 21177
* This target does not yet support ISD::BRCONDTWOWAYChris Lattner2005-04-091-0/+1
| | | | llvm-svn: 21163
* 64b: Expand S/UREMNate Begeman2005-04-091-7/+27
| | | | | | | | | 32b: No longer pattern match fneg(fsub(fmul)) as fnmsub Pattern match fsub a, mul(b, c) as fnmsub Pattern match fadd a, mul(b, c) as fmadd Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8% llvm-svn: 21161
* Optimized code sequences for setcc reg, 0Nate Begeman2005-04-071-4/+77
| | | | | | Optimized code sequence for (a < 0) ? b : 0 llvm-svn: 21150
* PowerPC zero extends setcc resultsChris Lattner2005-04-071-0/+1
| | | | llvm-svn: 21147
* Pattern match bitfield insert, which helps shift long by immediate, amongNate Begeman2005-04-061-15/+152
| | | | | | other things. llvm-svn: 21127
* Fixed version of optimized integer divide is now fixed. Calculate theNate Begeman2005-04-061-13/+9
| | | | | | | quotient, not the remainder. Also, make sure to remove the old div operand from the ExprMap and let SelectExpr insert the new one. llvm-svn: 21111
* Turn off the div -> mul optimization until it works correctly 100% of theNate Begeman2005-04-061-5/+5
| | | | | | time. llvm-svn: 21105
* Add support for MULHS and MULHU nodesNate Begeman2005-04-061-20/+192
| | | | | | | | Have LegalizeDAG handle SREM and UREM for us Codegen SDIV and UDIV by constant as a multiply by magic constant instead of integer divide, which is very slow. llvm-svn: 21104
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