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* Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen2010-04-051-8/+0
| | | | | | | | | | | | | | | | | | | When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. llvm-svn: 100384
* Move target independent td files from lib/Target/ to include/llvm/Target so ↵Evan Cheng2008-11-241-1/+1
| | | | | | they can be distributed along with the header files. llvm-svn: 59953
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Switch PPC return lower to use an autogenerated CC description.Chris Lattner2007-03-061-0/+6
| | | | llvm-svn: 34940
* Honor cpu directive, take two.Jim Laskey2006-12-121-17/+39
| | | | llvm-svn: 32492
* Rename some subtarget features. A CPU now can *have* 64-bit instructions,Chris Lattner2006-06-161-3/+3
| | | | | | can in 32-bit mode we can choose to optionally *use* 64-bit registers. llvm-svn: 28824
* getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng2006-05-181-9/+0
| | | | llvm-svn: 28378
* Remove PointerType from class TargetEvan Cheng2006-05-171-3/+0
| | | | llvm-svn: 28368
* add callee saved vector regsChris Lattner2006-03-161-1/+2
| | | | llvm-svn: 26805
* Mark instructions that are cracked by the PPC970 decoder as such.Chris Lattner2006-03-131-3/+2
| | | | llvm-svn: 26720
* Several big changes:Chris Lattner2006-03-121-3/+18
| | | | | | | | | | | 1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. llvm-svn: 26719
* Add a subtarget feature for the stfiwx instruction. I know the G5 has it,Chris Lattner2006-02-281-2/+4
| | | | | | | but I don't know what other PPC impls do. If someone could update the proc table, I would appreciate it :) llvm-svn: 26421
* Subtarget feature can now set any variable to any valueEvan Cheng2006-01-271-5/+5
| | | | llvm-svn: 25678
* Add attribute name and type to SubtargetFeatures.Jim Laskey2005-10-261-5/+5
| | | | llvm-svn: 24012
* mark this as betaChris Lattner2005-10-231-1/+1
| | | | llvm-svn: 23906
* rearrange things a bit so that instructions can use subtarget features in theChris Lattner2005-10-231-11/+9
| | | | | | future. llvm-svn: 23902
* improve -help outputChris Lattner2005-10-231-5/+5
| | | | llvm-svn: 23892
* Add g3 back to the mix and reorder to irritate them anal folk. Actually, it'sJim Laskey2005-10-221-9/+10
| | | | | | | to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
* 64-bit reg support should not be enabled by default, as support isn't complete.Chris Lattner2005-10-211-2/+2
| | | | llvm-svn: 23878
* Plugin new subtarget backend into the build.Jim Laskey2005-10-211-18/+25
| | | | llvm-svn: 23870
* Added InstrSchedClass to each of the PowerPC Instructions.Jim Laskey2005-10-191-0/+37
| | | | | | | Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
* Rename PowerPC*.td -> PPC*.tdChris Lattner2005-10-141-2/+2
| | | | llvm-svn: 23740
* Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.tdChris Lattner2005-10-141-0/+38
llvm-svn: 23738
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