summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips
Commit message (Collapse)AuthorAgeFilesLines
...
* [mips] Add precondition asserts to the expandLoadInst/expandStoreInst. NFCSimon Atanasyan2018-05-241-12/+23
| | | | llvm-svn: 333162
* [mips] Cleanup the code a bit. NFCSimon Atanasyan2018-05-241-15/+25
| | | | llvm-svn: 333161
* Silence warnings introduced with r333093Petar Jovanovic2018-05-231-1/+1
| | | | | | | | r333093 introduced several warnings (-Wlogical-not-parentheses, -Wbool-compare). Adding parentheses in MipsSEInstrInfo::isCopyInstr() to silence it. llvm-svn: 333097
* [X86][MIPS][ARM] New machine instruction property 'isMoveReg'Petar Jovanovic2018-05-2313-16/+115
| | | | | | | | | | | | | This property is needed in order to follow values movement between registers. This property is used in TII to implement method that returns true if simple copy like instruction is recognized, along with source and destination machine operands. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D45204 llvm-svn: 333093
* [mips] Merge MipsLongBranch and MipsHazardSchedule passesAleksandar Beserminji2018-05-225-328/+337
| | | | | | | | | | | | | | MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it potentially breaks some jumps, so they have to be expanded to long branches. When some branch is expanded to long branch, it potentially creates a hazard situation, which should be fixed by adding nops. New pass is called MipsBranchExpansion, it combines these two passes, and runs them alternately until one of them reports no changes were made. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332977
* [mips] Correct the predicates of the cache and pref instructionsSimon Dardis2018-05-223-16/+14
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46949 llvm-svn: 332970
* MC: Separate creating a generic object writer from creating a target object ↵Peter Collingbourne2018-05-214-18/+14
| | | | | | | | | | | | | writer. NFCI. With this we gain a little flexibility in how the generic object writer is created. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47045 llvm-svn: 332868
* MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an ↵Peter Collingbourne2018-05-212-12/+12
| | | | | | | | | | | | | MCObjectWriter. NFCI. To make this work I needed to add an endianness field to MCAsmBackend so that writeNopData() implementations know which endianness to use. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47035 llvm-svn: 332857
* [mips] Revert Merge MipsLongBranch and MipsHazardSchedule passesAleksandar Beserminji2018-05-215-332/+327
| | | | | | | | Revert this patch due buildbot failure. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332837
* [mips] Merge MipsLongBranch and MipsHazardSchedule passesAleksandar Beserminji2018-05-215-327/+332
| | | | | | | | | | | | | | MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it potentially breaks some jumps, so they have to be expanded to long branches. When some branch is expanded to long branch, it potentially creates a hazard situation, which should be fixed by adding nops. New pass is called MipsBranchExpansion, it combines these two passes, and runs them alternately until one of them reports no changes were made. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332834
* [mips] Add microMIPSR6 ll/sc instructions.Simon Dardis2018-05-206-15/+64
| | | | | | | | | | Previously the compiler was using the microMIPSR3 variants, incorrectly. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46948 llvm-svn: 332820
* MC: Change the streamer ctors to take an object writer instead of a stream. ↵Peter Collingbourne2018-05-185-16/+22
| | | | | | | | | | | | | | NFCI. The idea is that a client that wants split dwarf would create a specific kind of object writer that creates two files, and use it to create the streamer. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47050 llvm-svn: 332749
* [mips] Add support for Global INValidate ASEPetar Jovanovic2018-05-1713-2/+199
| | | | | | | | | | | | | | | | | | This includes Instructions: ginvi, ginvt, Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv Attribute: ginv .MIPS.abiflags: GINV (0x20000) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D46268 llvm-svn: 332624
* [mips] Simplify some of the predicate scopes for (negative) multiply add/sub ↵Simon Dardis2018-05-161-23/+20
| | | | | | instructions (NFCI) llvm-svn: 332464
* [mips] Join existing scopes for DecoderNamespace (NFCI)Simon Dardis2018-05-161-6/+3
| | | | llvm-svn: 332462
* [mips] Add support for isBranchOffsetInRange and use it for MipsLongBranchSimon Dardis2018-05-164-14/+205
| | | | | | | | | | | | Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
* [mips] Mark select instructions correctlySimon Dardis2018-05-153-151/+192
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46702 llvm-svn: 332364
* [mips] Fix formatting of floating point conversion patternsSimon Dardis2018-05-151-8/+8
| | | | llvm-svn: 332341
* [mips] Add disassembly support for comparison instructionsSimon Dardis2018-05-151-4/+6
| | | | llvm-svn: 332340
* [mips] Fix predicates of mfc1, mtc1 instructionsSimon Dardis2018-05-152-28/+22
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46692 llvm-svn: 332339
* [mips] Fix the predicates of round, ceiling, floor and trunc.Simon Dardis2018-05-142-38/+36
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-1417-143/+158
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [mips] Correct the predicates of indexed floating point stores and loads.Simon Dardis2018-05-142-14/+14
| | | | | | | | | | Also, fix the register class for microMIPS. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46689 llvm-svn: 332227
* [mips] Initialize the long branch pass for testing purposesSimon Dardis2018-05-123-2/+8
| | | | llvm-svn: 332172
* [mips] Rename Filler to MipsDelaySlotFiller and initialize the passSimon Dardis2018-05-113-26/+44
| | | | llvm-svn: 332102
* [mips] Enable disassembly of fused (negative) multiply add/sub instructionsSimon Dardis2018-05-112-37/+45
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46392 llvm-svn: 332097
* [mips] Accept 32-bit offsets for ld/sd/lld commandsSimon Atanasyan2018-05-102-4/+4
| | | | | | | | | | | | This is a follow up to the rL330983. The patch teaches ld, sd, and lld commands accept 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. In fact, these commands should accept 64-bit offsets, but so large offsets require another command expanding and will be supported by a separate patch. Differential Revision: https://reviews.llvm.org/D46629 llvm-svn: 331997
* [mips] Accept 32-bit offsets for lh and lhu commandsSimon Atanasyan2018-05-102-4/+4
| | | | | | | | | | This is a follow up to the rL330983. The patch teaches lh and lhu commands accepts 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. Differential Revision: https://reviews.llvm.org/D46513 llvm-svn: 331996
* [mips] Correct the predicates of cvt.fmt.fmt instructionsSimon Dardis2018-05-102-23/+24
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46390 llvm-svn: 331969
* [mips] Move conditional moves out of isCodeGenOnlySimon Dardis2018-05-093-28/+30
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46389 llvm-svn: 331863
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-095-6/+8
| | | | | | | | | | | | | | | | | | Because we create a new kind of debug instruction, DBG_LABEL, we need to check all passes which use isDebugValue() to check MachineInstr is debug instruction or not. When expelling debug instructions, we should expel both DBG_VALUE and DBG_LABEL. So, I create a new function, isDebugInstr(), in MachineInstr to check whether the MachineInstr is debug instruction or not. This patch has no new test case. I have run regression test and there is no difference in regression test. Differential Revision: https://reviews.llvm.org/D45342 Patch by Hsiangkai Wang. llvm-svn: 331844
* [mips][msa] Pattern match the splat.d instructionStefan Maksimovic2018-05-082-11/+32
| | | | | | | | | | | Introduced a new pattern for matching splat.d explicitly. Both splat.d and splati.d can now be generated from the @llvm.mips.splat.d intrinsic depending on whether an immediate value has been passed. Differential Revision: https://reviews.llvm.org/D45683 llvm-svn: 331771
* [mips] Mark various memory instructions as being in microMIPS (NFC)Simon Dardis2018-05-081-10/+9
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46388 llvm-svn: 331756
* [mips] Correct clo/clz predicatesSimon Dardis2018-05-082-22/+19
| | | | | | | | Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46125 llvm-svn: 331754
* [mips] Correct the predicates of sign extension instructionsSimon Dardis2018-05-044-29/+5
| | | | | | | | | | And eliminatw the duplication of those instructions for microMIPS32r6. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46117 llvm-svn: 331526
* [MIPS] Fix DIV/DIVU scheduling classes.Clement Courbet2018-05-021-2/+2
| | | | | | https://reviews.llvm.org/D46356. llvm-svn: 331354
* Revert "[mips] Correct the predicates of sign extension instructions"Simon Dardis2018-05-024-5/+29
| | | | | | | | | I accidently committed this patch after asking for a review, but it has not been reviewed yet. This reverts r331346. llvm-svn: 331348
* [mips] Correct the predicates of sign extension instructionsSimon Dardis2018-05-024-29/+5
| | | | | | And eliminate the duplication of those instructions for microMIPS32r6. llvm-svn: 331346
* [mips] Correct the predicates for shifts.Simon Dardis2018-05-022-23/+21
| | | | | | | | Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-018-52/+52
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* Reland r331175: "[mips] Fix the predicates of jump and branch and link ↵Simon Dardis2018-05-014-50/+69
| | | | | | | | | | | | | | | | instructions" The previous version of this patch restricted the 'jal' instruction to MIPS and microMIPSr3. microMIPS32r6 does not have this instruction and instead uses jal as an alias for balc. Original commit message: > Reviewers: smaksimovic, atanasyan, abeserminji > > Differential Revision: https://reviews.llvm.org/D46114 > llvm-svn: 331259
* IWYU for llvm-config.h in llvm, additions.Nico Weber2018-04-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See r331124 for how I made a list of files missing the include. I then ran this Python script: for f in open('filelist.txt'): f = f.strip() fl = open(f).readlines() found = False for i in xrange(len(fl)): p = '#include "llvm/' if not fl[i].startswith(p): continue if fl[i][len(p):] > 'Config': fl.insert(i, '#include "llvm/Config/llvm-config.h"\n') found = True break if not found: print 'not found', f else: open(f, 'w').write(''.join(fl)) and then looked through everything with `svn diff | diffstat -l | xargs -n 1000 gvim -p` and tried to fix include ordering and whatnot. No intended behavior change. llvm-svn: 331184
* Revert "[mips] Fix the predicates of jump and branch and link instructions"Simon Dardis2018-04-303-67/+50
| | | | | | | | That commit broke one of the LLD builders, reverting while I investigate. This patch reverts r331175. llvm-svn: 331178
* [mips] Fix the predicates of jump and branch and link instructionsSimon Dardis2018-04-303-50/+67
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46114 llvm-svn: 331175
* [mips] Fix microMIPS loads and stores.Simon Dardis2018-04-302-33/+41
| | | | | | | | | | | Previously these instructions were unselectable and instead were generated through the instruction mapping tables. Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46055 llvm-svn: 331165
* [mips] Analyze and provide selection patterns microMIPSR6 branchesSimon Dardis2018-04-272-1/+49
| | | | | | | | | | | These branches were previously unanalyzable and unselectable. Add them and recognize how to generate their inverses. Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46113 llvm-svn: 331050
* [mips] Fix how compiler fuse instructions to fmadd/fmsubAleksandar Beserminji2018-04-275-9/+30
| | | | | | | | | | This patch makes compiler does not fuse fmul and fadd/fsub into fmadd/fmsub by default. Instead, -fp-contract=fast option can be used when such behavior is desired. Differential Revision: https://reviews.llvm.org/D46057 llvm-svn: 331033
* [mips] Add support for Virtualization ASEPetar Jovanovic2018-04-2713-24/+357
| | | | | | | | | | | | | | | | | | | This includes Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0, Assembler directives: .set virt, .set novirt, .module virt, .module novirt Attribute: virt .MIPS.abiflags: VZ (0x100) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D44905 llvm-svn: 331024
* [mips] Accept 32-bit offsets for lb and lbu commandsSimon Atanasyan2018-04-262-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `lb` and `lbu` commands accepts 16-bit signed offsets. But GAS accepts larger offsets for these commands. If an offset does not fit in 16-bit range, `lb` command is translated into lui/lb or lui/addu/lb series. It's interesting that initially LLVM assembler supported this feature, but later it was broken. This patch restores support for 32-bit offsets. It replaces `mem_simm16` operand for `LB` and `LBu` definitions by the new `mem_simmptr` operand. This operand is intended to check that offset fits to the same size as using for pointers. Later we will be able to extend this rule and accepts 64-bit offsets when it is possible. Some issues remain: - The regression also affects LD, SD, LH, LHU commands. I'm going to fix them by a separate patch. - GAS accepts any 32-bit values as an offset. Now LLVM accepts signed 16-bit values and this patch extends the range to signed 32-bit offsets. In other words, the following code accepted by GAS and still triggers an error by LLVM: ``` lb $4, 0x80000004 # gas lui a0, 0x8000 lb a0, 4(a0) ``` - In case of 64-bit pointers GAS accepts a 64-bit offset and translates it to the li/dsll/lb series of commands. LLVM still rejects it. Probably this feature has never been implemented in LLVM. This issue is for a separate patch. ``` lb $4, 0x800000001 # gas li a0, 0x8000 dsll a0, a0, 0x14 lb a0, 4(a0) ``` Differential Revision: https://reviews.llvm.org/D45020 llvm-svn: 330983
* [mips] Correct the definitions of some control instructionsSimon Dardis2018-04-263-39/+36
| | | | | | | | | | | | | | Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
OpenPOWER on IntegriCloud