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| author | Simon Dardis <simon.dardis@mips.com> | 2018-05-08 09:50:37 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-05-08 09:50:37 +0000 |
| commit | 7563624fcba42032e95442bb4e8f439f5edf7669 (patch) | |
| tree | 20781fc3767bd577fbd5b3ec83022e42005e5b2b /llvm/lib/Target/Mips | |
| parent | 3366dcfe1f8586e89a1ce5cf5fbffbd4d9c42235 (diff) | |
| download | bcm5719-llvm-7563624fcba42032e95442bb4e8f439f5edf7669.tar.gz bcm5719-llvm-7563624fcba42032e95442bb4e8f439f5edf7669.zip | |
[mips] Correct clo/clz predicates
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D46125
llvm-svn: 331754
Diffstat (limited to 'llvm/lib/Target/Mips')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 37 |
2 files changed, 19 insertions, 22 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index a16cc98e9c5..1b0df6690cc 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -921,9 +921,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Count Leading def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>, - ISA_MIPS32; + ISA_MICROMIPS; def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>, - ISA_MIPS32; + ISA_MICROMIPS; /// Sign Ext In Register Instructions. def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index ab5a13ac587..37d6eb96740 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -2279,27 +2279,24 @@ def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>, ISA_MIPS1_NOT_32R6_64R6; def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>, ISA_MIPS1_NOT_32R6_64R6; -let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug - AdditionalPredicates = [NotInMicroMips] in { -def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>, - ISA_MIPS1_NOT_32R6_64R6; -def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, - ISA_MIPS1_NOT_32R6_64R6; - -/// Sign Ext In Register Instructions. -def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, - SEB_FM<0x10, 0x20>, ISA_MIPS32R2; -def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, - SEB_FM<0x18, 0x20>, ISA_MIPS32R2; -} - -/// Count Leading -def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>, - ISA_MIPS32_NOT_32R6_64R6; -def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>, - ISA_MIPS32_NOT_32R6_64R6; - let AdditionalPredicates = [NotInMicroMips] in { + def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>, + ISA_MIPS1_NOT_32R6_64R6; + def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, + ISA_MIPS1_NOT_32R6_64R6; + + /// Sign Ext In Register Instructions. + def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, + SEB_FM<0x10, 0x20>, ISA_MIPS32R2; + def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, + SEB_FM<0x18, 0x20>, ISA_MIPS32R2; + + /// Count Leading + def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>, + ISA_MIPS32_NOT_32R6_64R6; + def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>, + ISA_MIPS32_NOT_32R6_64R6; + /// Word Swap Bytes Within Halfwords def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>, ISA_MIPS32R2; |
