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* [MIPS GlobalISel] Legalize i64 addPetar Jovanovic2018-10-082-1/+50
| | | | | | | | | | Custom legalize s64 G_ADD for MIPS32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D52652 llvm-svn: 344007
* [TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints()Jonas Paulsson2018-10-051-2/+0
| | | | | | | | | | | | Finally all targets are enabling multiple regalloc hints, so the hook to disable this can now be removed. NFC. Review: Simon Pilgrim https://reviews.llvm.org/D52316 llvm-svn: 343851
* [MIPS GlobalISel] Lower i64 argumentsPetar Jovanovic2018-09-282-61/+110
| | | | | | | | | | | | | Lower integer arguments larger then 32 bits for MIPS32. setMostSignificantFirst is used in order for G_UNMERGE_VALUES and G_MERGE_VALUES to always hold registers in same order, regardless of endianness. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D52409 llvm-svn: 343315
* [mips] Add support MIPS r6 Debian triplesSimon Atanasyan2018-09-271-4/+11
| | | | | | | | | | | | | | | | | | | Debian uses different triples for MIPS r6 and paths. Here we use SubArch to determine whether it is r6, if we found `r6' in CPU section of triple. These new triples include: mipsisa32r6-linux-gnu mipsisa32r6el-linux-gnu mipsisa64r6-linux-gnuabi64 mipsisa64r6el-linux-gnuabi64 mipsisa64r6-linux-gnuabin32 mipsisa64r6el-linux-gnuabin32 Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D50857 llvm-svn: 343185
* llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song2018-09-271-1/+1
| | | | | | | | | | | | Summary: The convenience wrapper in STLExtras is available since rL342102. Reviewers: dblaikie, javed.absar, JDevlieghere, andreadb Subscribers: MatzeB, sanjoy, arsenm, dschuff, mehdi_amini, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, javed.absar, gbedwell, jrtc27, mgrang, atanasyan, steven_wu, george.burgess.iv, dexonsmith, kristina, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D52573 llvm-svn: 343163
* [mips] Correct MUL pattern for mips64Stefan Maksimovic2018-09-252-1/+4
| | | | | | | | Guard existing pattern with a predicate, introduce a new one for revision 6. Differential Revision: https://reviews.llvm.org/D51684 llvm-svn: 342946
* [Mips][FastISel] Fix selectBranch on icmp i1Petar Jovanovic2018-09-241-0/+5
| | | | | | | | | | | | | | The r337288 tried to fix result of icmp i1 when its input is not sanitized by falling back to DagISel. While it now produces the correct result for bit 0, the other bits can still hold arbitrary value which is not supported by MipsFastISel branch lowering. This patch fixes the issue by falling back to DagISel in this case. Patch by Dragan Mladjenovic. Differential Revision: https://reviews.llvm.org/D52045 llvm-svn: 342884
* [mips] Provide more detailed description for MIPS targets. NFCSimon Atanasyan2018-09-221-4/+5
| | | | llvm-svn: 342799
* [mips] Remove obsoleted "experimental" tag from MIPS 64-bit targets. NFCSimon Atanasyan2018-09-221-2/+2
| | | | llvm-svn: 342798
* [mips][microMIPS] Extending size reduction pass with MOVEPSimon Atanasyan2018-09-192-11/+109
| | | | | | | | | | | The patch extends size reduction pass for MicroMIPS. Two MOVE instructions are transformed into one MOVEP instrucition. Patch by Milena Vujosevic Janicic. Differential revision: https://reviews.llvm.org/D52037 llvm-svn: 342572
* [mips][microMIPS] Fix the definition of MOVEP instructionSimon Atanasyan2018-09-197-134/+117
| | | | | | | | | | | | The patch fixes definition of MOVEP instruction. Two registers are used instead of register pairs. This is necessary as machine verifier cannot handle register pairs. Patch by Milena Vujosevic Janicic. Differential revision: https://reviews.llvm.org/D52035 llvm-svn: 342571
* [mips] Fix MIPS N32 ABI triples supportSimon Atanasyan2018-09-173-2/+9
| | | | | | | | | | | | Add support mips64(el)-linux-gnuabin32 triples, and set them to N32. Debian architecture name mipsn32/mipsn32el are also added. Set UseIntegratedAssembler for N32 if we can detect it. Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51408 llvm-svn: 342416
* [mips] Enable the mnemonic spell correctorSimon Atanasyan2018-09-131-1/+7
| | | | | | | | | | | | This implements suggesting alternative mnemonics when an invalid one is specified. For example `addru $9, $6, 17767` leads to the following error message: error: unknown instruction, did you mean: add, addiu, addu, maddu? Differential revision: https://reviews.llvm.org/D40646 llvm-svn: 342119
* [MIPS] Fix illegal type assert in single-float modeSimon Atanasyan2018-09-111-3/+8
| | | | | | | | | | | | An fp_to_sint node would be incorrectly lowered to a TruncIntFP node in single-float mode. This would trigger an "Unexpected illegal type!" assert. Patch by Dan Ravensloft. Differential revision: https://reviews.llvm.org/D51810 llvm-svn: 341952
* [mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instructionSimon Atanasyan2018-09-111-0/+3
| | | | | | | | | | | | | | | | | | | | | MIPS ISAs start to support third operand for the `rdhwr` instruction starting from Revision 6. But LLVM generates assembler code with three-operands version of this instruction on any MIPS64 ISA. The third operand is always zero, so in case of direct code generation we get correct code. This patch fixes the bug by adding an instruction alias. The same alias already exists for 32-bit ISA. Ideally, we also need to reject three-operands version of the `rdhwr` instruction in an assembler code if ISA revision is less than 6. That is a task for a separate patch. This fixes PR38861 (https://bugs.llvm.org/show_bug.cgi?id=38861) Differential revision: https://reviews.llvm.org/D51773 llvm-svn: 341919
* [MIPS GlobalISel] Select icmpPetar Jovanovic2018-09-103-0/+89
| | | | | | | | | | Select 32bit integer compare instructions for MIPS32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D51489 llvm-svn: 341840
* [mips] Disable the selection of mixed microMIPS/MIPS codeSimon Atanasyan2018-09-034-8/+40
| | | | | | | | | | | | | This patch modifies hasStandardEncoding() / inMicroMipsMode() / inMips16Mode() methods of the MipsSubtarget class so only one can be true at any one time. That prevents the selection of microMIPS and MIPS instructions and patterns that are defined in TableGen files at the same time. A few new patterns and instruction definitions hae been added to keep test cases passed. Differential revision: https://reviews.llvm.org/D51483 llvm-svn: 341338
* [mips] Fix `mtc1` and `mfc1` definitions for microMIPS R6Simon Atanasyan2018-08-312-5/+5
| | | | | | | | | | | | | | | The `mtc1` and `mfc1` definitions in the MipsInstrFPU.td have MMRel, but do not have StdMMR6Rel tags. When these instructions are emitted for microMIPS R6 targets, `Mips::MipsR62MicroMipsR6` nor `Mips::Std2MicroMipsR6` cannot find correct op-codes and as a result the backend uses mips32 variant of the instructions encoding. The patch fixes this problem by adding the StdMMR6Rel tag and check instructions encoding in the test case. Differential revision: https://reviews.llvm.org/D51482 llvm-svn: 341221
* Make TargetInstrInfo::isCopyInstr return true for regular COPY-instructionsAlexander Ivchenko2018-08-304-12/+21
| | | | | | | | | | | ..Move all target-dependent checks into new isCopyInstrImpl method. This change allows us to treat MoveReg-type instructions and generic COPY instruction in the same way Differential Revision: https://reviews.llvm.org/D49913 llvm-svn: 341072
* [mips] Fix microMIPS unconditional branch offset handlingSimon Atanasyan2018-08-291-2/+7
| | | | | | | | | | | | | | MipsSEInstrInfo class defines for internal purpose unconditional branches as Mips::B nad Mips:J even in case of microMIPS code generation. Under some conditions that leads to the bug - for rather long branch which fits to Mips jump instruction offset size, but does not fit to microMIPS jump offset size, we generate 'short' branch and later show an error 'out of range PC16 fixup' after check in the isBranchOffsetInRange routine. Differential revision: https://reviews.llvm.org/D50615 llvm-svn: 340932
* [mips] Involves microMIPS's jump in the analyzable branch setSimon Atanasyan2018-08-291-1/+1
| | | | | | | | | Involves microMIPS's jump in the analyzable branch set to reduce some code patterns. Differential revision: https://reviews.llvm.org/D50613 llvm-svn: 340931
* [mips] Prevent shrink-wrap for BuildPairF64, ExtractElementF64 when they use $spVladimir Stefanovic2018-08-292-5/+24
| | | | | | | | | | | | | | | | For a certain combination of options, BuildPairF64_{64}, ExtractElementF64{_64} may be expanded into instructions using stack. Add implicit operand $sp for such cases so that ShrinkWrapping doesn't move prologue setup below them. Fixes MultiSource/Benchmarks/MallocBench/cfrac for '--target=mips-img-linux-gnu -mcpu=mips32r6 -mfpxx -mnan=2008' and '--target=mips-img-linux-gnu -mcpu=mips32r6 -mfp64 -mnan=2008 -mno-odd-spreg'. Differential Revision: https://reviews.llvm.org/D50986 llvm-svn: 340927
* [mips] Add missing instructionsAleksandar Beserminji2018-08-291-0/+32
| | | | | | | | Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920
* [MIPS GlobalISel] Legalize i8 and i16 addPetar Jovanovic2018-08-261-1/+3
| | | | | | | | | | | | Legalize G_ADD for types smaller than i32. LegalizationArtifactCombiner replaces extend instructions with appropriate bitwise instructions. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D51213 llvm-svn: 340697
* [MIPS GlobalISel] Lower i8 and i16 argumentsPetar Jovanovic2018-08-232-55/+139
| | | | | | | | | | | | Lower integer arguments smaller than i32. Support both register and stack arguments. Define setLocInfo function for setting LocInfo field in ArgLocs vector. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D51031 llvm-svn: 340572
* [mips] Handle missing CondCodesStefan Maksimovic2018-08-221-0/+29
| | | | | | | | | | | | | | | | | | | | Add patterns for unhandled CondCode enumerables: SETEQ, SETGE, SETGT, SETLE, SETLT, SETNE. Stated at the ISD::CondCode enum declaration: `All of these (except for the 'always folded ops') should be handled for floating point.` Add patterns which use these nodes, same as corresponding 'ordered' CondCode nodes. Referring to 'Ordered means that neither operand is a QNAN' we assume it is safe to match ex. SETLT node to the same instruction as SETOLT. Differential Revision: https://reviews.llvm.org/D50757 llvm-svn: 340392
* [MIPS GlobalISel] Select bitwise instructionsPetar Jovanovic2018-08-212-0/+9
| | | | | | | | | | Select bitwise instructions for i32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D50183 llvm-svn: 340258
* [MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth2018-08-161-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a generically extensible collection of extra info attached to a `MachineInstr`. The primary change here is cleaning up the APIs used for setting and manipulating the `MachineMemOperand` pointer arrays so chat we can change how they are allocated. Then we introduce an extra info object that using the trailing object pattern to attach some number of MMOs but also other extra info. The design of this is specifically so that this extra info has a fixed necessary cost (the header tracking what extra info is included) and everything else can be tail allocated. This pattern works especially well with a `BumpPtrAllocator` which we use here. I've also added the basic scaffolding for putting interesting pointers into this, namely pre- and post-instruction symbols. These aren't used anywhere yet, they're just there to ensure I've actually gotten the data structure types correct. I'll flesh out support for these in a subsequent patch (MIR dumping, parsing, the works). Finally, I've included an optimization where we store any single pointer inline in the `MachineInstr` to avoid the allocation overhead. This is expected to be the overwhelmingly most common case and so should avoid any memory usage growth due to slightly less clever / dense allocation when dealing with >1 MMO. This did require several ergonomic improvements to the `PointerSumType` to reasonably support the various usage models. This also has a side effect of freeing up 8 bits within the `MachineInstr` which could be repurposed for something else. The suggested direction here came largely from Hal Finkel. I hope it was worth it. ;] It does hopefully clear a path for subsequent extensions w/o nearly as much leg work. Lots of thanks to Reid and Justin for careful reviews and ideas about how to do all of this. Differential Revision: https://reviews.llvm.org/D50701 llvm-svn: 339940
* [mips] Remove dead code from MipsPassConfigSimon Atanasyan2018-08-161-4/+0
| | | | | | | | | | Found by GCC's -Wunused-function. Patch by Kim Gräsman. Differential revision: https://reviews.llvm.org/D50612 llvm-svn: 339847
* [mips] Handle branch expansion corner casesAleksandar Beserminji2018-08-072-93/+160
| | | | | | | | | | | | When potential jump instruction and target are in the same segment, use jump instruction with immediate field. In cases where offset does not fit immediate value of a bc/j instructions, offset is stored into register, and then jump register instruction is used. Differential Revision: https://reviews.llvm.org/D48019 llvm-svn: 339126
* [GlobalISel] Fix typo with missed override specifierAlexander Ivchenko2018-08-021-1/+1
| | | | llvm-svn: 338689
* [GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per ↵Alexander Ivchenko2018-08-022-9/+19
| | | | | | | | | | Value This is logical continuation of https://reviews.llvm.org/D46018 (r332449) Differential Revision: https://reviews.llvm.org/D49660 llvm-svn: 338685
* [MIPS GlobalISel] Select global addressPetar Jovanovic2018-08-013-0/+31
| | | | | | | | | | Select G_GLOBAL_VALUE for position dependent code. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D49803 llvm-svn: 338499
* Remove trailing spaceFangrui Song2018-07-305-12/+12
| | | | | | sed -Ei 's/[[:space:]]+$//' include/**/*.{def,h,td} lib/**/*.{cpp,h} llvm-svn: 338293
* DAG: Add calling convention argument to calling convention funcsMatt Arsenault2018-07-284-6/+10
| | | | | | | | This seems like a pretty glaring omission, and AMDGPU wants to treat kernels differently from other calling conventions. llvm-svn: 338194
* [mips] Sign extend i32 return values on MIPS64Stefan Maksimovic2018-07-264-0/+64
| | | | | | | | | | | | | Override getTypeForExtReturn so that functions returning an i32 typed value have it sign extended on MIPS64. Also provide patterns to get rid of unneeded sign extensions for arithmetic instructions which implicitly sign extend their results. Differential Revision: https://reviews.llvm.org/D48374 llvm-svn: 338019
* [MIPS GlobalISel] Lower pointer argumentsPetar Jovanovic2018-07-252-1/+3
| | | | | | | | | | | | Add support for lowering pointer arguments. Changing type from pointer to integer is already done in MipsTargetLowering::getRegisterTypeForCallingConv. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D49419 llvm-svn: 337912
* [mips] Replace custom parsing logic for data directives by the ↵Simon Atanasyan2018-07-253-42/+12
| | | | | | | | | | | | | | | | | | | | | `addAliasForDirective` The target independent AsmParser doesn't recognise .hword, .word, .dword which are required for Mips. Currently MipsAsmParser recognises these through dispatch to MipsAsmParser::parseDataDirective. This contains equivalent logic to AsmParser::parseDirectiveValue. This patch allows reuse of AsmParser::parseDirectiveValue by making use of addAliasForDirective to support .hword, .word and .dword. Original patch provided by Alex Bradbury at D47001 was modified to fix handling of microMIPS symbols. The `AsmParser::parseDirectiveValue` calls either `EmitIntValue` or `EmitValue`. In this patch we override `EmitIntValue` in the `MipsELFStreamer` to clear a pending set of microMIPS symbols. Differential revision: https://reviews.llvm.org/D49539 llvm-svn: 337893
* [mips] Fix local dynamic TLS with Sym64Simon Atanasyan2018-07-246-22/+20
| | | | | | | | | | | | | | | | For the final DTPREL addition, rather than a lui/daddiu/daddu triple, LLVM was erronously emitting a daddiu/daddiu pair, treating the %dtprel_hi as if it were a %dtprel_lo, since Mips::Hi expands unshifted for Sym64. Instead, use a new TlsHi node and, although unnecessary due to the exact structure of the nodes emitted, use TlsHi for local exec too to prevent future bugs. Also garbage-collect the unused TprelLo and TlsGd nodes, and TprelHi since its functionality is provided by the new common TlsHi node. Patch by James Clarke. Differential revision: https://reviews.llvm.org/D49259 llvm-svn: 337827
* [mips] Factor out register class selection for global base register. NFCSimon Atanasyan2018-07-211-18/+20
| | | | | | | Factor out register class selection for global base register into a separate function to escape long chain of ternary operators. llvm-svn: 337647
* [mips] Move out the WrapperPat declaration from the NotInMicroMips predicateSimon Atanasyan2018-07-211-5/+4
| | | | | | | | | | | | | | | This is a follow-up to the rL335185. Those commit adds some WrapperPat patterns for microMIPS target. But declaration of the WrapperPat class is under the NotInMicroMips predicate and microMIPS patterns cannot be selected because predicate (Subtarget->inMicroMipsMode()) && (!Subtarget->inMicroMipsMode()) is always false. This change move out the WrapperPat class declaration from the NotInMicroMips predicate and enables microMIPS WrapperPat patterns. Differential revision: https://reviews.llvm.org/D49533 llvm-svn: 337646
* [mips] Fix predicate for the MipsTruncIntFP patternSimon Atanasyan2018-07-181-1/+1
| | | | | | | | | This is a follow-up to the rL337171. This patch fixes regression introduced by the r337171 and enables MipsTruncIntFP pattern. Differential revision: https://reviews.llvm.org/D49469 llvm-svn: 337392
* [Mips][FastISel] Fix handling of icmp with i1 typePetar Jovanovic2018-07-171-0/+4
| | | | | | | | | | | The Mips FastISel back-end does not extend i1 values while lowering icmp. Ensure that we bail into DAG ISel when handling this case. Patch by Dragan Mladjenovic. Differential Revision: https://reviews.llvm.org/D49290 llvm-svn: 337288
* [mips] Eliminate the usage of hasStdEnc in MipsPat.Simon Atanasyan2018-07-167-161/+206
| | | | | | | | | | | Instead, the pattern is tagged with the correct predicate when it is declared. Some patterns have been duplicated as necessary. Patch by Simon Dardis. Differential revision: https://reviews.llvm.org/D48365 llvm-svn: 337171
* [MIPS GlobalISel] Select instructions to load and store i32 on stackPetar Jovanovic2018-07-163-2/+88
| | | | | | | | | | | Add code for selection of G_LOAD, G_STORE, G_GEP, G_FRAMEINDEX and G_CONSTANT. Support loads and stores of i32 values. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D48957 llvm-svn: 337168
* CodeGen: Remove pipeline dependencies on StackProtector; NFCMatthias Braun2018-07-133-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | This re-applies r336929 with a fix to accomodate for the Mips target scheduling multiple SelectionDAG instances into the pass pipeline. PrologEpilogInserter and StackColoring depend on the StackProtector analysis being alive from the point it is run until PEI, which requires that they are all scheduled in the same FunctionPassManager. Inserting a (machine) ModulePass between StackProtector and PEI results in these passes being in separate FunctionPassManagers and the StackProtector is not available for PEI. PEI and StackColoring don't use much information from the StackProtector pass, so transfering the required information to MachineFrameInfo is cleaner than keeping the StackProtector pass around. This commit moves the SSP layout information to MFI instead of keeping it in the pass. This patch set (D37580, D37581, D37582, D37583, D37584, D37585, D37586, D37587) is a first draft of the pagerando implementation described in http://lists.llvm.org/pipermail/llvm-dev/2017-June/113794.html. Patch by Stephen Crane <sjc@immunant.com> Differential Revision: https://reviews.llvm.org/D49256 llvm-svn: 336964
* [mips] Mark standard encoded instructions as not being in MIPS16eSimon Atanasyan2018-07-122-3/+3
| | | | | | | | | | | Mark standard encoded instructions and pseudo "standard encoded" as not being in MIPS16e by default. Patch by Simon Dardis. Differential revision: https://reviews.llvm.org/D48379 llvm-svn: 336893
* [mips] Update the P5600 scheduler model not to use instruction itineraries.Simon Atanasyan2018-07-111-63/+93
| | | | | | | | | | | | | | | This mostly brings the P5600 scheduler model to a mostly complete status. There are a number of instructions which trigger the `error:'MipsP5600Model' lacks information for` error. These are certain codegen only instructions relating to MIPS64 which can be addressed by using the correct predicates for them. That will be done in a full-up patch. Patch by Simon Dardis. Differential revision: https://reviews.llvm.org/D45245 llvm-svn: 336802
* [mips] Remove dead code. NFCSimon Atanasyan2018-07-115-38/+0
| | | | llvm-svn: 336777
* [mips] Addition of the [d]rem and [d]remu instructionsStefan Maksimovic2018-07-093-25/+116
| | | | | | | | | | | | | Related to http://reviews.llvm.org/D15772 Depends on http://reviews.llvm.org/D16889 Adds [D]REM[U] instructions. Patch By: Srdjan Obucina Contributions from: Simon Dardis Differential Revision: https://reviews.llvm.org/D17036 llvm-svn: 336545
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