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* [mips] Change type of accumulator registers to Untyped. Add two more accumulatorAkira Hatanaka2013-03-291-7/+30
| | | | | | | | register classes for Mips64 and DSP-ASE. No functionality changes. llvm-svn: 178328
* [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.Akira Hatanaka2013-03-295-43/+74
| | | | | | No functionality changes. llvm-svn: 178327
* [mips] Add parameter Alignment to MipsFrameLowering's constructor.Akira Hatanaka2013-03-293-5/+4
| | | | | | No functionality changes. llvm-svn: 178326
* [Mips Assembler] Add support for OR macro with imediate opperandJack Carter2013-03-282-1/+6
| | | | | | | | | Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic llvm-svn: 178316
* [Mips Assembler] Add alias definitions for jalJack Carter2013-03-282-0/+7
| | | | | | | | | | | Mips assembler allows following to be used as aliased instructions: jal $rs for jalr $rs jal $rd,$rd for jalr $rd,$rs This patch provides alias definitions in td files and test cases to show the usage. Contributer: Vladimir Medic llvm-svn: 178304
* Fix comment.Akira Hatanaka2013-03-251-3/+3
| | | | llvm-svn: 177899
* Allow the register scavenger to spill multiple registersHal Finkel2013-03-221-1/+1
| | | | | | | | | | | | | | | | | | This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. llvm-svn: 177774
* Fix the invalid opcode for Mips branch instructions in the assemblerJack Carter2013-03-221-4/+6
| | | | | | | | | | | | | | | For mips a branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Previously, the code generator did not perform the shift of the immediate branch offset which resulted in wrong instruction opcode. This patch fixes the issue. Contributor: Vladimir Medic llvm-svn: 177687
* This patch that enables the Mips assembler to use symbols for offset for ↵Jack Carter2013-03-222-17/+154
| | | | | | | | | | | | instructions This patch uses the generated instruction info tables to identify memory/load store instructions. After successful matching and based on the operand type and size, it generates additional instructions to the output. Contributor: Vladimir Medic llvm-svn: 177685
* This patch enables the Mips .set directive to define aliasesJack Carter2013-03-211-6/+93
| | | | | | | | | | | | | | | | The .set directive in the Mips the assembler can be used to set the value of a symbol to an expression. This changes the symbol's value and type to conform to the expression's. Syntax: .set symbol, expression This patch implements the parsing of the above syntax and enables the parser to use defined symbols when parsing operands. Contributor: Vladimir Medic llvm-svn: 177667
* Silence anonymous type in anonymous union warnings.Eric Christopher2013-03-151-18/+23
| | | | llvm-svn: 177135
* Remove some unused variables to clean the Clang -Werror buildDavid Blaikie2013-03-141-2/+0
| | | | | | (these were added in r177089) llvm-svn: 177129
* [mips] Set isAllocatable bit of unallocatable register classes to 0.Akira Hatanaka2013-03-141-8/+13
| | | | llvm-svn: 177128
* Add a new method which enables one to change register classes.Reed Kotler2013-03-141-0/+8
| | | | | | | | | | | | See the Mips16ISetLowering.cpp patch to see a use of this. For now now the extra code in Mips16ISetLowering.cpp is a nop but is used for test purposes. Mips32 registers are setup and then removed and then the Mips16 registers are setup. Normally you need to add register classes and then call computeRegisterProperties. llvm-svn: 177120
* Provide the register scavenger to processFunctionBeforeFrameFinalizedHal Finkel2013-03-141-1/+2
| | | | | | | | | | | | | Add the current PEI register scavenger as a parameter to the processFunctionBeforeFrameFinalized callback. This change is necessary in order to allow the PowerPC target code to set the register scavenger frame index after the save-area offset adjustments performed by processFunctionBeforeFrameFinalized. Only after these adjustments have been made is it possible to estimate the size of the stack frame. llvm-svn: 177108
* [mips] Fix filename in comment and delete unnecessary lines of code.Akira Hatanaka2013-03-141-5/+1
| | | | | | No functionality changes. llvm-svn: 177104
* Add back lines which were accidentally deleted in CMakeLists.txt.Akira Hatanaka2013-03-141-0/+2
| | | | llvm-svn: 177096
* [mips] Define function MipsSEDAGToDAGISel::selectAddESubE.Akira Hatanaka2013-03-142-31/+31
| | | | | | No intended functionality changes. llvm-svn: 177095
* [mips] Rename functions and variables to start with proper case.Akira Hatanaka2013-03-147-57/+57
| | | | llvm-svn: 177092
* Add header file MipsISelDAGToDAG.h.Akira Hatanaka2013-03-141-0/+93
| | | | llvm-svn: 177090
* [mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is forAkira Hatanaka2013-03-146-648/+900
| | | | | | | | mips16 and MipsSEDAGToDAGISel is for mips32/64. No functionality changes. llvm-svn: 177089
* [mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is forAkira Hatanaka2013-03-139-878/+1106
| | | | | | | | mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
* [mips] Rename function and variable names to start with proper case. Fix typos.Akira Hatanaka2013-03-123-571/+493
| | | | | | Delete commented-out code. llvm-svn: 176844
* DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard2013-03-081-1/+4
| | | | | | | | | | | | | LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. llvm-svn: 176694
* [mips] Custom-legalize BR_JT.Akira Hatanaka2013-03-062-1/+33
| | | | | | In N64-static, GOT address is needed to compute the branch address. llvm-svn: 176580
* [mips] Remove android calling convention.Akira Hatanaka2013-03-054-19/+1
| | | | | | | This calling convention was added just to handle functions which return vector of floats. The fix committed in r165585 solves the problem. llvm-svn: 176530
* [mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 getsAkira Hatanaka2013-03-052-40/+55
| | | | | | returned in registers $2 and $4. llvm-svn: 176527
* [mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctlyAkira Hatanaka2013-03-052-15/+74
| | | | | | handle fp128 returns. llvm-svn: 176523
* [mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floatingAkira Hatanaka2013-03-052-6/+15
| | | | | | point registers. llvm-svn: 176521
* [mips] Correct handling of fp128 (long double) formals and read long doubleAkira Hatanaka2013-03-052-9/+79
| | | | | | parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
* [mips] Print move instructions.Akira Hatanaka2013-03-042-2/+2
| | | | | | "move $4, $5" is printed instead of "or $4, $5, $zero". llvm-svn: 176455
* Mips specific inline assembler constraint 'R'Jack Carter2013-03-041-0/+5
| | | | | | | 'R' An address that can be sued in a non-macro load or store. This patch includes a positive test case. llvm-svn: 176452
* Mips ISD typoJia Liu2013-03-041-1/+1
| | | | llvm-svn: 176426
* [mips] Fix inefficient code generation.Akira Hatanaka2013-03-013-1/+16
| | | | | | | | | | | | | This patch eliminates the need to emit a constant move instruction when this pattern is matched: (select (setgt a, Constant), T, F) The pattern above effectively turns into this: (conditional-move (setlt a, Constant + 1), F, T) llvm-svn: 176384
* Fix indentation.Akira Hatanaka2013-03-011-15/+10
| | | | llvm-svn: 176380
* Fix PR10475Michael Liao2013-03-011-1/+1
| | | | | | | | | | | | | | - ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. llvm-svn: 176364
* [mips] Remove unused option. Fix 80-column violations.Akira Hatanaka2013-03-011-16/+8
| | | | llvm-svn: 176330
* [mips] Add the capability to search delay slot filling instructions inAkira Hatanaka2013-03-011-32/+303
| | | | | | | | successor basic blocks. Currently this is off by default. llvm-svn: 176329
* [mips] Do not add SecondLastInst to list BranchInstrs if there is only oneAkira Hatanaka2013-03-011-2/+2
| | | | | | | | terminator. No functionality change. llvm-svn: 176326
* [mips] Define an overloaded version of function MipsInstrInfo::AnalyzeBranchAdd.Akira Hatanaka2013-03-012-74/+103
| | | | | | | | This function will be used later when the capability to search delay slot filling instructions in successor blocks is added. No intended functionality changes. llvm-svn: 176325
* [mips] Add options to disable searching backward and in successor blocks.Akira Hatanaka2013-03-011-0/+12
| | | | llvm-svn: 176321
* [mips] Add capability to search in the forward direction for instructions thatAkira Hatanaka2013-03-011-23/+92
| | | | | | | | can fill the delay slot. Currently, this is off by default. llvm-svn: 176320
* [mips] Define helper function searchRangeAkira Hatanaka2013-03-011-9/+29
| | | | | | No functionality change. llvm-svn: 176318
* [mips] Rename function findDelayInstr to searchBackward.Akira Hatanaka2013-03-011-3/+3
| | | | llvm-svn: 176317
* [mips] Define class MemDefsUses.Akira Hatanaka2013-03-011-23/+126
| | | | | | | This class tracks dependence between memory instructions using underlying objects of memory operands. llvm-svn: 176313
* Fix cut/paste error in a comment.Reed Kotler2013-02-271-1/+1
| | | | llvm-svn: 176165
* Add the skeleton for the Mips constant island pass.Reed Kotler2013-02-274-0/+89
| | | | | | | It will only be used for Mips 16 at this time. llvm-svn: 176161
* [mips] Use class RegDefsUses to track register defs and uses.Akira Hatanaka2013-02-261-89/+82
| | | | | | No functionality change. llvm-svn: 176070
* Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.Reed Kotler2013-02-255-69/+70
| | | | llvm-svn: 176007
* Make psuedo FEXT_T8I816_ins into a custom emitter.Reed Kotler2013-02-245-61/+39
| | | | llvm-svn: 176002
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