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authorJack Carter <jack.carter@imgtec.com>2013-03-04 21:33:15 +0000
committerJack Carter <jack.carter@imgtec.com>2013-03-04 21:33:15 +0000
commit0e149b04f6902447595a006b75167b3aec3dc555 (patch)
tree7148be56abed1348825d87fbf1aca0517d4cc6e1 /llvm/lib/Target/Mips
parent8764fe7d9aa133b037528f1d118e6a6259f2f0ee (diff)
downloadbcm5719-llvm-0e149b04f6902447595a006b75167b3aec3dc555.tar.gz
bcm5719-llvm-0e149b04f6902447595a006b75167b3aec3dc555.zip
Mips specific inline assembler constraint 'R'
'R' An address that can be sued in a non-macro load or store. This patch includes a positive test case. llvm-svn: 176452
Diffstat (limited to 'llvm/lib/Target/Mips')
-rw-r--r--llvm/lib/Target/Mips/MipsISelLowering.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 310a82e7817..cbcc18c7e51 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -3880,6 +3880,8 @@ getConstraintType(const std::string &Constraint) const
case 'l':
case 'x':
return C_RegisterClass;
+ case 'R':
+ return C_Memory;
}
}
return TargetLowering::getConstraintType(Constraint);
@@ -3928,6 +3930,9 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
if (isa<ConstantInt>(CallOperandVal))
weight = CW_Constant;
break;
+ case 'R':
+ weight = CW_Memory;
+ break;
}
return weight;
}
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