summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips
Commit message (Collapse)AuthorAgeFilesLines
* [mips] [IAS] Allow .set assignments for already defined symbols.Toma Tabacu2015-04-071-5/+1
| | | | | | | | | | | | | | | | Summary: This is not possible when using the IAS for MIPS, but it is possible when using the IAS for other architectures and when using GAS for MIPS. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8578 llvm-svn: 234316
* [mips] Implement eliminateCallFramePseudoInstr() in MipsFrameLowering. NFC.Vasileios Kalintiris2015-04-026-41/+22
| | | | | | | | | | | | | | | | | Summary: Avoid duplicate code in Mips16FrameLowering and MipsSEFrameLowering by providing an implementation of the eliminateCallFramePseudoInstr() function from their base class. Depends on D8640. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8641 llvm-svn: 233909
* [mips] Expose adjustStackPtr() from MipsInstrInfo. NFC.Vasileios Kalintiris2015-04-025-10/+8
| | | | | | | | | | | | | | | | | Summary: adjustStackPtr() is implemented from both MipsSEInstrInfo and Mips16InstrInfo. It makes sense to expose this function from MipsInstrInfo and avoid explicit casting in some cases. Depends on D8638. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8640 llvm-svn: 233905
* [mips] Make sure that we don't adjust the stack pointer by zero amount.Vasileios Kalintiris2015-04-022-0/+6
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8638 llvm-svn: 233904
* Replace the MCSubtargetInfo parameter with a Triple when creatingEric Christopher2015-03-311-3/+3
| | | | | | | an MCInstPrinter. Update all callers and use where we wanted a Triple previously. llvm-svn: 233648
* Remove unused Target argument from MCInstPrinter ctor functions.Eric Christopher2015-03-301-2/+1
| | | | llvm-svn: 233607
* Remove more superfluous .str() and replace std::string concatenation with Twine.Yaron Keren2015-03-301-1/+1
| | | | | | Following r233392, http://llvm.org/viewvc/llvm-project?rev=233392&view=rev. llvm-svn: 233555
* [mips] Support 9-bit offsets for the 'R' inline assembly memory constraint.Daniel Sanders2015-03-301-1/+14
| | | | | | | | | | | | | | | | | | | Summary: The 'R' constraint is actually supposed to be much more complicated than this and is defined in terms of whether it will cause macro expansion in the assembler. 'R' is getting less useful due to architecture changes and ought to be replaced by other constraints. We therefore implement 9-bit offsets which will work for all subtargets and all instructions. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8440 llvm-svn: 233537
* [MCInstPrinter] Enable MCInstPrinter to change its behavior based on theAkira Hatanaka2015-03-272-2/+3
| | | | | | | | | | | | | | | | | | | | per-function subtarget. Currently, code-gen passes the default or generic subtarget to the constructors of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which enables some targets (AArch64, ARM, and X86) to change their instprinter's behavior based on the subtarget feature bits. Since the backend can now use different subtargets for each function, instprinter has to be changed to use the per-function subtarget rather than the default subtarget. This patch takes the first step towards enabling instprinter to change its behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the various print methods table-gen auto-generates. I will follow up with changes to instprinters of AArch64, ARM, and X86. llvm-svn: 233411
* [mips] Move the setATReg definition inside the MipsAssemblerOptions class. NFC.Toma Tabacu2015-03-261-9/+7
| | | | | | | | | | | | | | Summary: This groups all of the MipsAssemblerOptions functionality together, making it more reader-friendly. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8445 llvm-svn: 233271
* [mips] Support 16-bit offsets for 'm' inline assembly memory constraint.Daniel Sanders2015-03-241-1/+9
| | | | | | | | | | | | Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8435 llvm-svn: 233086
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-244-67/+63
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* [mips] Simplify boolean expressions in Mips target with `clang-tidy`Simon Atanasyan2015-03-242-11/+7
| | | | | | | | | | No functional changes. Patch by Richard Thomson. Differential Revision: http://reviews.llvm.org/D8522 llvm-svn: 233065
* [mips] Distinguish 'R', 'ZC', and 'm' inline assembly memory constraint.Daniel Sanders2015-03-246-12/+111
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Previous behaviour of 'R' and 'm' has been preserved for now. They will be improved in subsequent commits. The offset permitted by ZC varies according to the subtarget since it is intended to match the restrictions of the pref, ll, and sc instructions. The restrictions on these instructions are: * For microMIPS: 12-bit signed offset. * For Mips32r6/Mips64r6: 9-bit signed offset. * Otherwise: 16-bit signed offset. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8414 llvm-svn: 233063
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-244-63/+67
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used.Benjamin Kramer2015-03-233-1/+4
| | | | llvm-svn: 232998
* Purge unused includes throughout libSupport.Benjamin Kramer2015-03-232-1/+3
| | | | | | NFC. llvm-svn: 232976
* Fix sign extension for MIPS64 in makeLibCall functionPetar Jovanovic2015-03-232-0/+11
| | | | | | | | | | | | Fixing sign extension in makeLibCall for MIPS64. In MIPS64 architecture all 32 bit arguments (int, unsigned int, float 32 (soft float)) must be sign extended. This fixes test "MultiSource/Applications/oggenc/". Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D7791 llvm-svn: 232943
* Remove the target independent TargetMachine::getSubtarget andEric Christopher2015-03-211-1/+1
| | | | | | | | | | | | | | | | | | | TargetMachine::getSubtargetImpl routines. This keeps the target independent code free of bare subtarget calls while the remainder of the backends are migrated, or not if they don't wish to support per-function subtargets as would be needed for function multiversioning or LTO of disparate cpu subarchitecture types, e.g. clang -msse4.2 -c foo.c -emit-llvm -o foo.bc clang -c bar.c -emit-llvm -o bar.bc llvm-link foo.bc bar.bc -o baz.bc llc baz.bc and get appropriate code for what the command lines requested. llvm-svn: 232885
* Grab the cached subtarget off of the MachineFunction.Eric Christopher2015-03-211-5/+4
| | | | llvm-svn: 232878
* Grab a subtarget off of a MipsTargetMachine rather than aEric Christopher2015-03-212-7/+11
| | | | | | | bare target machine in preparation for the TargetMachine bare getSubtarget/getSubtargetImpl calls going away. llvm-svn: 232877
* Split the object streamer callback in one per file format.Rafael Espindola2015-03-195-22/+23
| | | | | | | | | | | | | There are two main advantages to doing this * Targets that only need to handle one of the formats specially don't have to worry about the others. For example, x86 now only registers a constructor for the COFF streamer. * Changes to the arguments passed to one format constructor will not impact the other formats. llvm-svn: 232699
* two or more, use a for.Rafael Espindola2015-03-181-82/+34
| | | | llvm-svn: 232688
* [mips] Add itineraries for ext and ins instructions.Kai Nacke2015-03-182-2/+6
| | | | | | | | | | | Currently, there are no itineraries defined for ext and ins instructions. This patch adds these itineraries and uses them in the instruction definitions. Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D7209 llvm-svn: 232613
* [mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.Toma Tabacu2015-03-171-0/+2
| | | | | | | | | | | | | | | | Summary: This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58". This should work for all MIPS ISAs. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8284 llvm-svn: 232473
* Pass in a "const Triple &T" instead of a raw StringRef.Rafael Espindola2015-03-161-2/+2
| | | | llvm-svn: 232429
* Remove unused argument. NFC.Rafael Espindola2015-03-161-3/+3
| | | | llvm-svn: 232428
* There is only one Asm streamer, there is no need for targets to register it.Rafael Espindola2015-03-161-13/+13
| | | | | | | Instead, have the targets register a TargetStreamer to be use with the asm streamer (if any). llvm-svn: 232423
* Fix uses of reserved identifiers starting with an underscore followed by an ↵David Blaikie2015-03-161-4/+3
| | | | | | | | | uppercase letter This covers essentially all of llvm's headers and libs. One or two weird cases I wasn't sure were worth/appropriate to fix. llvm-svn: 232394
* [MIPS] Fix justify error for small structuresPetar Jovanovic2015-03-161-1/+1
| | | | | | | | | | | | | | | Fix justify error for small structures bigger than 32 bits in fixed arguments for MIPS64 big endian. There was a problem when small structures are passed as fixed arguments. The structures that are bigger than 32 bits but smaller than 64 bits were not left justified properly on MIPS64 big endian. This is fixed by shifting the value to make it left justified when appropriate. Patch by Aleksandar Beserminji. Differential Revision: http://reviews.llvm.org/D8174 llvm-svn: 232382
* Make each target map all inline assembly memory constraints to ↵Daniel Sanders2015-03-161-0/+6
| | | | | | | | | | | | | | | | | | | InlineAsm::Constraint_m. NFC. Summary: This is instead of doing this in target independent code and is the last non-functional change before targets begin to distinguish between different memory constraints when selecting code for the ISD::INLINEASM node. Next, each target will individually move away from the idea that all memory constraints behave like 'm'. Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8173 llvm-svn: 232373
* [mips] [IAS] Outline NOP creation. NFC.Toma Tabacu2015-03-161-22/+26
| | | | | | | | | | | | | | Summary: Make the code more readable by outlining NOP creation. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8320 llvm-svn: 232371
* [mips] Remove trivial header for the MipsModuleISelDAGToDAG pass. NFC.Vasileios Kalintiris2015-03-144-60/+20
| | | | llvm-svn: 232260
* [mips] Remove trivial header for the Mips16HardFloat pass. NFC.Vasileios Kalintiris2015-03-144-129/+97
| | | | llvm-svn: 232259
* [mips] Remove trivial header for the MipsOs16 pass. NFC.Vasileios Kalintiris2015-03-144-93/+72
| | | | llvm-svn: 232258
* Recommit r232027 with PR22883 fixed: Add infrastructure for support of ↵Daniel Sanders2015-03-135-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | multiple memory constraints. The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. PR22883 was caused the matching operands copying the whole of the operand flags for the matched operand. This included the constraint id which needed to be replaced with the operand number. This has been fixed with a conversion function. Following on from this, matching operands also used the operand number as the constraint id. This has been fixed by looking up the matched operand and taking it from there. llvm-svn: 232165
* [mips] [IAS] Refactor MipsTargetStreamer::emitMipsAbiFlags(). NFC.Toma Tabacu2015-03-132-7/+1
| | | | | | | | | | | | | | Summary: Make emitMipsAbiFlags a direct member of MipsTargetELFStreamer, as that's the only place where it's used, and remove the empty implementations from MipsTargetStreamer and MipsTargetAsmStreamer. Reviewers: dsanders, rafael Reviewed By: rafael Subscribers: rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D8199 llvm-svn: 232161
* Revert "r232027 - Add infrastructure for support of multiple memory constraints"Hal Finkel2015-03-122-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | This (r232027) has caused PR22883; so it seems those bits might be used by something else after all. Reverting until we can figure out what else to do. Original commit message: The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. llvm-svn: 232093
* Add infrastructure for support of multiple memory constraints.Daniel Sanders2015-03-122-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. Reviewers: hfinkel Reviewed By: hfinkel Subscribers: hfinkel, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8171 llvm-svn: 232027
* Remove some unnecessary forward declarations and put a couple moreEric Christopher2015-03-121-2/+0
| | | | | | where they're supposed to reside. llvm-svn: 232014
* Remove the need to cache the subtarget in the Mips TargetRegisterInfoEric Christopher2015-03-1210-26/+26
| | | | | | classes. llvm-svn: 232012
* Move the DataLayout to the generic TargetMachine, making it mandatory.Mehdi Amini2015-03-122-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: I don't know why every singled backend had to redeclare its own DataLayout. There was a virtual getDataLayout() on the common base TargetMachine, the default implementation returned nullptr. It was not clear from this that we could assume at call site that a DataLayout will be available with each Target. Now getDataLayout() is no longer virtual and return a pointer to the DataLayout member of the common base TargetMachine. I plan to turn it into a reference in a future patch. The only backend that didn't have a DataLayout previsouly was the CPPBackend. It now initializes the default DataLayout. This commit is NFC for all the other backends. Test Plan: clang+llvm ninja check-all Reviewers: echristo Subscribers: jfb, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8243 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231987
* Have getCallPreservedMask and getThisCallPreservedMask take aEric Christopher2015-03-114-5/+8
| | | | | | | MachineFunction argument so that we can grab subtarget specific features off of it. llvm-svn: 231979
* Have getCalleeSavedRegs take a non-null MachineFunction all theEric Christopher2015-03-112-3/+3
| | | | | | | | time. The target independent code was passing in one all the time and targets weren't checking validity before using. Update a few calls to pass in a MachineFunction where necessary. llvm-svn: 231970
* [mips][microMIPS] Make usage of NOT16 by code generatorJozef Kolek2015-03-112-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D7748 llvm-svn: 231963
* Remove the use of the subtarget in MCCodeEmitter creation andEric Christopher2015-03-102-4/+0
| | | | | | | update all ports accordingly. Required a couple of small rewrites in handling subtarget features during creation in PPC. llvm-svn: 231861
* DataLayout is mandatory, update the API to reflect it with references.Mehdi Amini2015-03-101-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that the DataLayout is a mandatory part of the module, let's start cleaning the codebase. This patch is a first attempt at doing that. This patch is not exactly NFC as for instance some places were passing a nullptr instead of the DataLayout, possibly just because there was a default value on the DataLayout argument to many functions in the API. Even though it is not purely NFC, there is no change in the validation. I turned as many pointer to DataLayout to references, this helped figuring out all the places where a nullptr could come up. I had initially a local version of this patch broken into over 30 independant, commits but some later commit were cleaning the API and touching part of the code modified in the previous commits, so it seemed cleaner without the intermediate state. Test Plan: Reviewers: echristo Subscribers: llvm-commits From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231740
* Remove an unused variable.Eric Christopher2015-03-101-1/+0
| | | | llvm-svn: 231730
* Add logical ops to Mips fast-iselReed Kotler2015-03-091-1/+89
| | | | | | | | | | | | | | | | | | | | | | Summary: Code is mostly copied from AArch64 port and modified where needed for Mips. This handles the "non" legal cases of logical ops. Legal cases are handled by tablegen patterns. Test Plan: Make check test logopm.ll All of test-suite passes at O0/O2 and mips32 r1/r2 with this new change. Reviewers: dsanders Reviewed By: dsanders Subscribers: echristo, llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D6599 llvm-svn: 231665
* Move unreferenced passes into the cpp fileBenjamin Kramer2015-03-096-88/+63
| | | | | | NFC. llvm-svn: 231661
OpenPOWER on IntegriCloud