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* [mips][ias] Move createCpRestoreMemOp to MipsTargetStreamer. NFC.Daniel Sanders2016-04-293-38/+57
| | | | | | | | | | | | | | | Summary: This removes the temporary call to isIntegratedAssemblerRequired() which was added recently. It's effect is now acheived directly in the MipsTargetStreamer hierarchy. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19715 llvm-svn: 268058
* [mips][FastISel] A store is not a load.Simon Dardis2016-04-291-1/+1
| | | | | | | | | | Correct trivial error. One of the failing tests from PR/27458. Reviewers: dsanders, vkalintiris, mcrosier Differential Review: http://reviews.llvm.org/D19726 llvm-svn: 268053
* [PATCH] [mips] Fix forbidden slot hazard handlingSimon Dardis2016-04-291-3/+11
| | | | | | | | | | | | | | | | | | MipsHazardSchedule has to determine what the next physical machine instruction is to decide whether to insert a nop. In case where a branch with a forbidden slot appears at the end of a basic block, first *real* instruction of the next physical basic block was determined using getFirstNonDebugInstr(). Unfortunately this only considers DBG_VALUEs and not other transient opcodes such as EHLABEL. As EHLABEL passes the SafeInForbiddenSlot predicate and the instruction after the EHLABEL can be a CTI, we observed test failures in the LNT testsuite. Reviewers: dsanders Differential Review: http://reviews.llvm.org/D19051 llvm-svn: 268052
* [mips][ias] Split expandMemInst between MipsAsmParser and ↵Daniel Sanders2016-04-293-66/+205
| | | | | | | | | | | | | | | | | | | | | | MipsTargetStreamer. Almost NFC. Summary: The portion in MipsAsmParser is responsible for figuring out which expansion to use, while the portion in MipsTargetStreamer is responsible for emitting it. This allows us to remove the call to isIntegratedAssemblerRequired() which is currently ensuring the effect of .cprestore only occurs when writing objects. The small functional change is that the memory offsets are now correctly printed as signed values. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19714 llvm-svn: 268042
* [mips][ias] Moved most instruction emission helpers to MipsTargetStreamer. NFC.Daniel Sanders2016-04-293-279/+325
| | | | | | | | | | | | | | | | | | | Summary: * Moved all the emit*() helpers to MipsTargetStreamer. * Moved createNop() to MipsTargetStreamer as emitNop() and emitEmptyDelaySlot(). This instruction has been split to distinguish between the 'nop' instruction and the nop used in delay slots which is sometimes a different nop to the 'nop' instruction (e.g. for short delay slots on microMIPS). * Moved createAddu() to MipsTargetStreamer as emitAddu(). * Moved createAppropriateDSLL() to MipsTargetStreamer as emitDSLL(). Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19712 llvm-svn: 268041
* [mips][ias] Make section sizes a multiple of the alignment.Daniel Sanders2016-04-291-0/+15
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19008 llvm-svn: 268036
* [mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructionsZlatko Buljan2016-04-294-33/+20
| | | | | | Differential Revision: http://reviews.llvm.org/D18645 llvm-svn: 268012
* [mips][atomics] Fix partword atomic binary operation implementationSimon Dardis2016-04-283-6/+15
| | | | | | | | | | | | | | | Currently Mips::emitAtomicBinaryPartword() does not properly respect the width of pointers. For MIPS64 this causes the memory address that the ll/sc sequence uses to be truncated. At runtime this causes a segmentation fault. This can be fixed by applying similar changes as r266204, so that a full 64bit pointer is loaded. Reviewers: dsanders Differential Review: http://reviews.llvm.org/D19651 llvm-svn: 267900
* [CodeGen] Default CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to Expand in ↵Craig Topper2016-04-281-4/+0
| | | | | | TargetLoweringBase. This is what the majority of the targets want and removes a bunch of code. Set it to Legal explicitly in the few cases where that's the desired behavior. llvm-svn: 267853
* [Mips] Add support for llvm.thread.pointer intrinsic.Marcin Koscielnicki2016-04-271-0/+4
| | | | | | | | This will be used to implement __builtin_thread_pointer in clang. Differential Revision: http://reviews.llvm.org/D19569 llvm-svn: 267743
* [mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU ↵Zlatko Buljan2016-04-275-20/+70
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16676 llvm-svn: 267694
* [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, ↵Zlatko Buljan2016-04-273-12/+41
| | | | | | | | SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
* [CodeGen] Add getBuildVector and getSplatBuildVector helpers. NFCI.Ahmed Bougacha2016-04-261-10/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D17176 llvm-svn: 267606
* [mips][microMIPS] Revert commit r267137Hrvoje Varga2016-04-254-14/+3
| | | | | | Commit r267137 was the reason for failing tests in LLVM test suite. llvm-svn: 267419
* [mips][microMIPS] Revert commit r266977Zlatko Buljan2016-04-254-26/+9
| | | | | | Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ... llvm-svn: 267418
* Fix an assertion that can never fire because the condition ANDed with the ↵Craig Topper2016-04-241-1/+1
| | | | | | string is just true or 1. llvm-svn: 267324
* [mips][microMIPS] Revert commit r266861.Zoran Jovanovic2016-04-2210-170/+8
| | | | | | Commit r266861 was the reason for failing tests in LLVM test suite. llvm-svn: 267166
* [mips] Fix select patterns for MIPS64Simon Dardis2016-04-221-1/+1
| | | | | | | | | | | | | | When targetting MIPS64R6 some of the patterns for select were guarded by a broken predicate. The predicate was supposed to test if a constant value could fit in a 16 bit zero-extended field. Instead the value was tested to fit in a 16 bit sign-extended field. For negative constants of native word width this resulted in wrong code generation. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D19378 llvm-svn: 267151
* [mips] Fix a small typo that would leave BLTZC out of getAnalyzableBrOpc().'Vasileios Kalintiris2016-04-221-1/+1
| | | | llvm-svn: 267149
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-04-224-3/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D19354 llvm-svn: 267137
* [mips][microMIPS] Add R_MICROMIPS_PC18_S3 relocationZoran Jovanovic2016-04-224-2/+23
| | | | | | Differential Revision: http://reviews.llvm.org/D15026 llvm-svn: 267130
* [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructionsZlatko Buljan2016-04-223-1/+60
| | | | | | Differential Revision: http://reviews.llvm.org/D18687 llvm-svn: 267114
* [mips][microMIPS] Implement ldpc instructionZoran Jovanovic2016-04-213-1/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D15009 llvm-svn: 266990
* [mips][microMIPS] Add R_MICROMIPS_PC19_S2 relocationZoran Jovanovic2016-04-214-2/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D14915 llvm-svn: 266988
* [mips][microMIPS] Add R_MICROMIPS_PC26_S1 relocationZoran Jovanovic2016-04-214-1/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D14822 llvm-svn: 266985
* [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructionsZlatko Buljan2016-04-211-5/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D18855 llvm-svn: 266980
* [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL ↵Zlatko Buljan2016-04-214-12/+25
| | | | | | | | instructions and add tests for LWM32 and SWM32 Differential Revision: http://reviews.llvm.org/D19150 llvm-svn: 266977
* [mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructionsZoran Jovanovic2016-04-204-24/+195
| | | | | | Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
* [mips][microMIPS]Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-04-2010-8/+172
| | | | | | Differential Revision: http://reviews.llvm.org/D18640 llvm-svn: 266861
* MipsAsmParser::loadImmediate(): Prune an obsolete \param in r266602. ↵NAKAMURA Takumi2016-04-201-1/+0
| | | | | | [-Wdocumentation] llvm-svn: 266841
* [mips][ias] Prevent double-filling of delay slots by generating '.set ↵Daniel Sanders2016-04-181-1/+8
| | | | | | | | | | | | | | | | | | noreorder' regions. Summary: When clang is given -save-temps or -via-file-asm, any inline assembly in the source is parsed twice. Once by the compiler, and again by the assembler. We must take care to ensure that this doesn't lead to double-filling delay slots. Reviewers: sdardis, vkalintiris Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19166 llvm-svn: 266608
* [mips][ias] Stream macro expansions to output instead of buffering them. NFC.Daniel Sanders2016-04-183-353/+336
| | | | | | | | | | | | | | | | | | | Summary: This will allows us to eliminate some magic numbers from the offset operand of branch instructions in favour of symbols and makes it possible to avoid double-filling delay slots when clang is given -save-temps. parseDirectiveCpRestore() is calling isIntegratedAssemblerRequired() for the moment since correctly pushing the generation of these instructions into the ELF target streamer is tricky enough to warrant a separate patch. Reviewers: sdardis, vkalintiris Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19164 llvm-svn: 266602
* [NFC] Header cleanupMehdi Amini2016-04-1817-28/+6
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [mips] More range-based for loops. NFC.Vasileios Kalintiris2016-04-153-10/+9
| | | | | | | There are still a couple more inside the MIPS target. I opted for a single commit in order to avoid spamming the list. llvm-svn: 266472
* [mips] Use range-based for loops and simplify slightly the code. NFC.Vasileios Kalintiris2016-04-151-9/+13
| | | | llvm-svn: 266471
* Summary:Simon Dardis2016-04-142-1/+7
| | | | | | | | | | Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. This patch was previous committed as r266055 as seemed to have caused some spurious test failures. They did not reappear after further local testing. llvm-svn: 266301
* [mips] Fix emitAtomicCmpSwapPartword to handle 64 bit pointers correctlyZoran Jovanovic2016-04-131-6/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D18995 llvm-svn: 266204
* [mips] Sign-extend i32 values truncated from previously zero-extended i32 ↵Vasileios Kalintiris2016-04-132-1/+49
| | | | | | | | | | | | | | | | | | | | values. Summary: This is a special case for MIPS64 because the architecture requires properly 32-bit sign-extended values in the register containers. Additionaly, we merge consecutive trunc + AssertZExt nodes in order to avoid unnecessary sign-extensions when the extension comes from a type smaller than i32. Reviewers: dsanders Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18893 llvm-svn: 266203
* [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, ↵Zlatko Buljan2016-04-139-42/+89
| | | | | | | | | | | | DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
* [mips][microMIPS] Fix for "Cannot copy registers" assertionHrvoje Varga2016-04-134-10/+24
| | | | | | | | Differential Revision: http://reviews.llvm.org/D17068 This changes contains fix for failing test-suite. So, this patch should hopefully work now. llvm-svn: 266171
* [mips] add assembler support for .set arch=octeonPetar Jovanovic2016-04-121-1/+1
| | | | | | | | | | | This patch enables assembler support for .set arch=octeon. It will fix issues with inline assembler when this directive is used. Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D18548 llvm-svn: 266081
* Revert "[mips] MIPSR6 Compact branch aliases"Simon Dardis2016-04-122-7/+1
| | | | | | | | This reverts commit r266055. ps4-buildslave2 is highlighting a failure. llvm-svn: 266061
* [mips] MIPSR6 Compact branch aliasesSimon Dardis2016-04-122-1/+7
| | | | | | | | | | | | Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D18856 llvm-svn: 266055
* [mips] Make Static a default relocation model for MIPS codegenPetar Jovanovic2016-04-111-3/+1
| | | | | | | | | | | | This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
* [mips] Trivial corrections to range checked immediates.Daniel Sanders2016-04-113-9/+8
| | | | | | | | | | | | | | Summary: SYNC has a 5-bit unsigned immediate. Move MIPS16-specific pcrel16 operand to Mips16 files. Reviewers: vkalintiris Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18755 llvm-svn: 265947
* [mips] Use range-based for loops. NFC.Vasileios Kalintiris2016-04-081-10/+16
| | | | llvm-svn: 265780
* [mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* ↵Zlatko Buljan2016-04-085-67/+188
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16454 llvm-svn: 265772
* RegisterScavenger: Take a reference as enterBasicBlock() argument.Matthias Braun2016-04-061-1/+1
| | | | | | | Make it obvious that the argument cannot be nullptr. Remove an unnecessary nullptr check in initRegState. llvm-svn: 265511
* [mips] MIPSR6 Compact jump supportSimon Dardis2016-04-054-67/+109
| | | | | | | | | | | | | | | This patch adds support for compact jumps similiar to the previous compact branch support for MIPSR6. Unlike compact branches, compact jumps do not have a forbidden slot. As MipsInstrInfo::getEquivalentCompactForm can determine the correct expansion for jumps and branches for both microMIPS and MIPSR6, remove the unnecessary distinction in the delay slot filler. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders llvm-svn: 265390
* Add MachineFunctionProperty checks for AllVRegsAllocated for target passesDerek Schuff2016-04-044-1/+20
| | | | | | | | | | | | | | Summary: This adds the same checks that were added in r264593 to all target-specific passes that run after register allocation. Reviewers: qcolombet Subscribers: jyknight, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18525 llvm-svn: 265313
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