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| author | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-04-21 11:32:40 +0000 |
|---|---|---|
| committer | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-04-21 11:32:40 +0000 |
| commit | dd4151504a798974c1e5c0de585dab64dc5f8165 (patch) | |
| tree | 7dceaa6cdef9e413672b225b1609505744a3a884 /llvm/lib/Target/Mips | |
| parent | 72ab8481fa6a0121430954bde8841baff2273d33 (diff) | |
| download | bcm5719-llvm-dd4151504a798974c1e5c0de585dab64dc5f8165.tar.gz bcm5719-llvm-dd4151504a798974c1e5c0de585dab64dc5f8165.zip | |
[mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions
Differential Revision: http://reviews.llvm.org/D18855
llvm-svn: 266980
Diffstat (limited to 'llvm/lib/Target/Mips')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 4384931345c..356f9852c18 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -2077,11 +2077,12 @@ def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32; class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary, FrmOther, asmstr>; -def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>; -def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>; -def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>; -def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>; - +let AdditionalPredicates = [NotInMicroMips] in { + def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>; + def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>; + def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>; + def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>; +} class CacheOp<string instr_asm, Operand MemOpnd> : InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint), !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther, |
