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* Convert more cases to isPositionIndependent(). NFC.Rafael Espindola2016-06-289-22/+22
| | | | llvm-svn: 274021
* Delete dead code. NFC.Rafael Espindola2016-06-283-12/+8
| | | | llvm-svn: 274020
* Fix typo.Rafael Espindola2016-06-271-1/+1
| | | | | | Thanks to Benjamin Kramer for noticing. llvm-svn: 273959
* Use isPositionIndependent(). NFC.Rafael Espindola2016-06-271-3/+2
| | | | llvm-svn: 273896
* [mips] Add instruction itineraries for LSA, DLSASimon Dardis2016-06-271-7/+6
| | | | | | | | Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D21679 llvm-svn: 273883
* Use the isPositionIndependent predicate. NFC.Rafael Espindola2016-06-271-6/+6
| | | | llvm-svn: 273870
* Add an explanation on how mips is special in here.Rafael Espindola2016-06-271-0/+11
| | | | llvm-svn: 273868
* [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV ↵Hrvoje Varga2016-06-279-60/+173
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16625 llvm-svn: 273850
* Mips: Fix access to private functions.Rafael Espindola2016-06-271-1/+1
| | | | llvm-svn: 273843
* [mips] Don't derive the default ABI from the CPU in the backend.Daniel Sanders2016-06-231-28/+3
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The backend has no reason to behave like a driver and should generally do as it's told (and error out if it can't) instead of trying to figure out what the API user meant. The default ABI is still derived from the arch component as a concession to backwards compatibility. API-users that previously passed an explicit CPU and a triple that was inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a different ABI to what they got before. However, it's expected that there are no such users on the basis that CodeGen has been asserting that the triple is consistent with the selected ABI for several releases. API-users that were consistent or passed '' or 'generic' as the CPU will see no difference. Reviewers: sdardis, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21466 llvm-svn: 273557
* [mips][ias] Integers are not registers.Daniel Sanders2016-06-231-6/+0
| | | | | | | | | | | | | | | | | | | Summary: When parseAnyRegister() encounters a symbol alias, it parses integers and adds a corresponding expression to the operand list. This is clearly wrong since the only operands that parseAnyRegister() should be accepting are registers. It's not clear why this code was added and there are no test cases that cover it. I think it might be leftover from when searchSymbolAlias() was more widely used. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21377 llvm-svn: 273555
* [mips] Fix dext/dins definitionsSimon Dardis2016-06-231-6/+8
| | | | | | | | | | | dext and dins, along with their 'm' and 'u' variants are defined in mips64r2, not mips64. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D21608 llvm-svn: 273549
* [SDAG] Remove FixedArgs parameter from CallLoweringInfo::setCalleeKrzysztof Parzyszek2016-06-221-1/+1
| | | | | | | | | | | The setCallee function will set the number of fixed arguments based on the size of the argument list. The FixedArgs parameter was often explicitly set to 0, leading to a lack of consistent value for non- vararg functions. Differential Revision: http://reviews.llvm.org/D20376 llvm-svn: 273403
* Delete more dead code.Rafael Espindola2016-06-211-51/+0
| | | | | | Found by gcc 6. llvm-svn: 273322
* Delete some dead code.Rafael Espindola2016-06-211-25/+0
| | | | | | Found by gcc 6. llvm-svn: 273303
* Replace silly uses of 'signed' with 'int'David Majnemer2016-06-211-1/+1
| | | | llvm-svn: 273244
* Untabify.NAKAMURA Takumi2016-06-201-2/+2
| | | | llvm-svn: 273129
* [mips] Emit a JALR with $rd equal to $zero, instead of a JR in MIPS32R6.Vasileios Kalintiris2016-06-181-15/+23
| | | | | | | | | | | | | | Summary: JR is an alias of JALR with $rd=0 in the R6 ISA. Also, this fixes recursive builds in MIPS32R6. Reviewers: dsanders, sdardis Subscribers: jfb, dschuff, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21370 llvm-svn: 273085
* [mips] Fix small typo. NFC.Vasileios Kalintiris2016-06-161-1/+1
| | | | llvm-svn: 272895
* [mips][mips16] Fix machine verifier errors about incorrect register classes ↵Daniel Sanders2016-06-167-161/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on load/stores. Summary: [ls][bh] and [ls][bh]u cannot use sp-relative addresses and must therefore lower frameindex nodes such that there is a copy to a CPU16Regs register. This is now done consistently using a separate addressing mode that does not permit frameindex nodes. As part of this I've had to remove an optimization that reduced the number of instructions needed to work around the lack of sp-relative addresses on [ls][bh] and [ls][bh]u. This optimization used one of the eight CPU16Regs registers as a copy of the stack pointer and it's implementation was the root cause of many of the register vs register class mismatches. lw/sw can use sp-relative addresses but we ought to ensure that we use the correct version of lw/sw internally for things like IAS. This is not currently the case and this change does not fix this. However, this change does clean it up sufficiently well to fix the machine verifier failures. Also removed irrelevant functions from stchar.ll. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21062 llvm-svn: 272882
* [llvm-objdump] Support detection of feature bits from the object and ↵Daniel Sanders2016-06-161-2/+3
| | | | | | | | | | | | | | | | | | | | implement this for Mips. Summary: The Mips implementation only covers the feature bits described by the ELF e_flags so far. Mips stores additional feature bits such as MSA in the .MIPS.abiflags section. Also fixed a small bug this revealed where microMIPS wouldn't add the EF_MIPS_MICROMIPS flag when using -filetype=obj. Reviewers: echristo, rafael Subscribers: rafael, mehdi_amini, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21125 llvm-svn: 272880
* [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructionsHrvoje Varga2016-06-165-86/+134
| | | | | | Differential Revision: http://reviews.llvm.org/D16917 llvm-svn: 272876
* [mips] Eliminate unused code for addrRegReg complex pattern. NFC.Vasileios Kalintiris2016-06-155-29/+0
| | | | | | | | | | Reviewers: dsanders, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21381 llvm-svn: 272794
* [mips] Replace AdditionalRequires<[IsGP64bit]> with GPR_64. NFC.Daniel Sanders2016-06-151-8/+4
| | | | | | | | | | | | Summary: Also fixed one case where HasMips64 was being used instead of IsGP64bit. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D21028 llvm-svn: 272771
* [mips] clang-format Mips16ISelDAGToDAG.{cpp,h}Daniel Sanders2016-06-152-52/+52
| | | | llvm-svn: 272768
* [mips][msa] Fix register/register-class mismatches in emitINSERT_DF_VIDX().Daniel Sanders2016-06-151-3/+6
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21068 llvm-svn: 272765
* [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and ↵Zlatko Buljan2016-06-154-132/+197
| | | | | | | | NOR instructions Differential Revision: http://reviews.llvm.org/D16719 llvm-svn: 272764
* [mips] Optimize stack pointer adjustments.Simon Dardis2016-06-143-4/+17
| | | | | | | | | | | | | | | | | | | | | Instead of always using addu to adjust the stack pointer when the size out is of the range of an addiu instruction, use subu so that a smaller constant can be generated. This can give savings of ~3 instructions whenever a function has a a stack frame whose size is out of range of an addiu instruction. This change may break some naive stack unwinders. Partially resolves PR/26291. Thanks to David Chisnall for reporting the issue. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D21321 llvm-svn: 272666
* [mips][atomics] Fix atomic instruction descriptions and uses.Simon Dardis2016-06-148-22/+107
| | | | | | | | | | | | | | PR27458 highlights that the MIPS backend does not have well formed MIR for atomic operations (among other errors). This patch adds expands and corrects the LL/SC descriptions and uses for MIPS(64). Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D19719 llvm-svn: 272655
* [mips][ias] Implement one N32 case (of two) for .cpsetup.Daniel Sanders2016-06-141-28/+27
| | | | | | | | | | | | | | | | | | | | | | This patch implements the N32 case where -mno-shared is in effect. The case where -mshared is in effect will be added later since doing that now requires additional changes to how we handle %hi(%neg(%gp_rel(foo))) expressions to emit the three relocations as three relocations (currently only one of the three would be emitted) which then requires further changes to our MCFixup handling. While we could fix both cases together, fixing the -mno-shared case allows us to fix the ELFCLASS bug (where N32 incorrectly uses ELFCLASS64 instead of ELFCLASS32) in a way that allows cpsetup.s to check for a correct output instead of another incorrect output. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D21131 llvm-svn: 272652
* [mips] MIPS32/64 itinerariesSimon Dardis2016-06-147-125/+300
| | | | | | | | | | | Itineraries for some pre MIPSR6 and EVA instructions. Some pseudo expanded instructions are marked as having no scheduling info. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D20418 llvm-svn: 272648
* [mips][dsp] Fix use without def on DSPCtrl registers read by rddsp intrinsic.Daniel Sanders2016-06-141-1/+2
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21063 llvm-svn: 272647
* [mips][msa] copyPhysReg() should not set RegState::Define on result of CTCMSA.Daniel Sanders2016-06-141-2/+5
| | | | | | | | | | | | | | Summary: The machine verifier reports 'Explicit operand marked as def' when it is manually specified even though it agrees with the operand info. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21065 llvm-svn: 272646
* Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.Benjamin Kramer2016-06-121-1/+1
| | | | | | No functionality change intended. llvm-svn: 272516
* Move instances of std::function.Benjamin Kramer2016-06-122-9/+9
| | | | | | Or replace with llvm::function_ref if it's never stored. NFC intended. llvm-svn: 272513
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-1215-97/+100
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* Remove a few gendered pronouns.Nico Weber2016-06-101-1/+1
| | | | llvm-svn: 272422
* [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructionsHrvoje Varga2016-06-099-13/+241
| | | | | | Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
* [mips][microMIPS] Add CodeGen support for SEL.*, SELEQZ, SELNEZ, SELEQZ.*, ↵Zlatko Buljan2016-06-094-80/+137
| | | | | | | | SELNEZ.* and CMP.condn.fmt instructions Differential Revision: http://reviews.llvm.org/D20862 llvm-svn: 272256
* [mips] Add a proper file header in MipsFastISel.cppVasileios Kalintiris2016-06-081-2/+15
| | | | llvm-svn: 272138
* [mips] EABI CodeGen is completely untested and seems to have bitrotted. ↵Daniel Sanders2016-06-037-69/+3
| | | | | | | | | | | | | | | | | | Remove it. Summary: There are no tests*, no EABI buildbots, and simple test cases do not work. * There is a single MIPS16 test using a mips*-gnueabi triple but this test doesn't test EABI and the triple doesn't cause EABI to be used. Reviewers: sdardis Subscribers: tberghammer, danalbert, srhines, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20906 llvm-svn: 271658
* [mips] Implement 'la' macro in PIC mode for O32.Daniel Sanders2016-06-034-35/+83
| | | | | | | | | | | | | | | | Summary: N32 support will follow in a later patch since the symbol version of 'la' incorrectly believes N32 to have 64-bit pointers and rejects it early. This fixes the three incorrectly expanded 'la' macros found in bionic. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20820 llvm-svn: 271644
* [mips] Enforce compact branch register restrictionsSimon Dardis2016-05-312-14/+66
| | | | | | | | | | | | | | | Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 llvm-svn: 271301
* [mips] bnec/beqc register constraint fixSimon Dardis2016-05-311-4/+6
| | | | | | | | | | | beqc and bnec cannot have $rs == $rt. Inhibit compact branch creation if that would occur. Reviewers: vkalintiris, dsanders Differential Revision: http://reviews.llvm.org/D20624 llvm-svn: 271260
* [mips] Weaken asm predicate for memory offsetsSimon Dardis2016-05-271-3/+7
| | | | | | | | | | | | The isMemWithSimmOffset predicate rejects relocations which is incorrect behaviour. Linkers and other tools should handle|warn|error when the field overflows. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D20727 llvm-svn: 270995
* Avoid some copies by using const references.Benjamin Kramer2016-05-271-1/+1
| | | | | | | clang-tidy's performance-unnecessary-copy-initialization with some manual fixes. No functional changes intended. llvm-svn: 270988
* [MIPS][LLVM-MC] Fix Disassemble of Negative OffsetSagar Thakur2016-05-241-8/+8
| | | | | | | | | | | Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
* ps][microMIPS] Add R_MICROMIPS_PC21_S1 relocationZoran Jovanovic2016-05-194-3/+21
| | | | | | Differential Revision: http://reviews.llvm.org/D15526 llvm-svn: 270048
* [mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine ↵Daniel Sanders2016-05-191-1/+1
| | | | | | | | | | | | | | verifier. Summary: Partially fixes PR27458 Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20330 llvm-svn: 270037
* [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructionsZlatko Buljan2016-05-194-4/+55
| | | | | | Differential Revision: http://reviews.llvm.org/D18352 llvm-svn: 270030
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