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* [cleanup] Re-sort all the #include lines in LLVM usingChandler Carruth2015-01-141-1/+1
| | | | | | | | | | | utils/sort_includes.py. I clearly haven't done this in a while, so more changed than usual. This even uncovered a missing include from the InstrProf library that I've added. No functionality changed here, just mechanical cleanup of the include order. llvm-svn: 225974
* Make the TargetMachine in MipsSubtarget a reference ratherEric Christopher2015-01-081-3/+3
| | | | | | than a pointer to make unifying code a bit easier. llvm-svn: 225459
* Remove unused variable, initializer, and accessor.Eric Christopher2014-12-191-1/+0
| | | | llvm-svn: 224650
* MipsABIInfo class is used in different libraries. Moving the files to ↵Vladimir Medic2014-12-171-1/+1
| | | | | | MCTargetDesc folder(LLVMMipsDesc library) prevents linkage errors. There are no functional changes. llvm-svn: 224427
* [mips] Add preliminary support for the MIPS II target.Vasileios Kalintiris2014-11-111-0/+1
| | | | | | | | | | | | | | | | | | | Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
* [mips] Replace MipsABIEnum with a MipsABIInfo class.Daniel Sanders2014-10-241-14/+8
| | | | | | | | | | | | | | | | | | | | | Summary: No functional change yet, it's just an object replacement for an enum. It will allow us to gather ABI information in a single place so that we can start testing for properties of the ABI's instead of the ABI itself. For example we will eventually be able to use: ABI.MinStackAlignmentInBytes() instead of: (isABI_N32() || isABI_N64()) ? 16 : 8 which is clearer and more maintainable. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3341 llvm-svn: 220568
* constify the TargetMachine being passed through the Mips subtargetEric Christopher2014-09-191-2/+3
| | | | | | creation. llvm-svn: 218169
* [mips] Remove inverted predicates from MipsSubtarget that were only used by ↵Daniel Sanders2014-09-101-3/+0
| | | | | | | | | | | | | | | | MipsCallingConv.td Summary: No functional change Reviewers: echristo, vmedic Reviewed By: echristo, vmedic Subscribers: echristo, llvm-commits Differential Revision: http://reviews.llvm.org/D5266 llvm-svn: 217494
* [mips] Move MipsTargetLowering::MipsCC::regSize() to ↵Daniel Sanders2014-09-091-0/+1
| | | | | | | | | | | | | | | | | | | | MipsSubtarget::getGPRSizeInBytes() Summary: The GPR size is more a property of the subtarget than that of the ABI so move this information to the MipsSubtarget. No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5009 llvm-svn: 217436
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-021-3/+0
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* [mips] Invert the abicalls feature bit to be noabicalls so that it's ↵Daniel Sanders2014-08-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | possible for -mno-abicalls to take effect. Also added the testcase that should have been in r215194. This behaviour has surprised me a few times now. The problem is that the generated MipsSubtarget::ParseSubtargetFeatures() contains code like this: if ((Bits & Mips::FeatureABICalls) != 0) IsABICalls = true; so '-abicalls' means 'leave it at the default' and '+abicalls' means 'set it to true'. In this case, (and the similar -modd-spreg case) I'd like the code to be IsABICalls = (Bits & Mips::FeatureABICalls) != 0; or possibly: if ((Bits & Mips::FeatureABICalls) != 0) IsABICalls = true; else IsABICalls = false; and preferably arrange for 'Bits & Mips::FeatureABICalls' to be true by default (on some triples). llvm-svn: 215211
* [mips] Initial implementation of -mabicalls/-mno-abicalls.Daniel Sanders2014-08-081-0/+4
| | | | | | | | | | | This patch implements the main rules for -mno-abicalls such as reserving $gp, and emitting the correct .option directive. Patch by Matheus Almeida and Toma Tabacu Differential Revision: http://reviews.llvm.org/D4231 llvm-svn: 215194
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-071-0/+3
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Nuke the old JIT.Rafael Espindola2014-08-071-3/+0
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-8/+14
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [mips] Don't use odd-numbered single precision registers for fastcc callingSasa Stankovic2014-07-291-0/+1
| | | | | | | | convention if -mno-odd-spreg is used. Differential Revision: http://reviews.llvm.org/D4682 llvm-svn: 214180
* Fundamentally change the MipsSubtarget replacement machinery:Eric Christopher2014-07-181-20/+1
| | | | | | | | | | | | | | | | | a) Move the replacement level decision to the target machine. b) Create additional subtargets at the TargetMachine level to cache and make replacement easy. c) Make the mips16 features obvious. d) Remove the override logic as it no longer does anything. e) Have MipsModuleDAGToDAGISel take only the target machine. f) Have the constant islands pass grab the current subtarget from the MachineFunction (via the TargetMachine) instead of caching it. g) Unconditionally initialize TLOF. h) Remove the old complicated subtarget based resetting and replace it with simple conditionals. llvm-svn: 213430
* Avoid caching the relocation model on the subtarget, this is forEric Christopher2014-07-181-6/+2
| | | | | | | | | | | two reasons: a) we're already caching the target machine which contains it, b) which relocation model you get is dependent upon whether or not you ask before MCCodeGenInfo is constructed on the target machine, so avoid any latent issues there. llvm-svn: 213420
* Avoid resetting the UseSoftFloat and FloatABIType on the TargetMachineEric Christopher2014-07-181-1/+5
| | | | | | | | | | Options struct and move the comment to inMips16HardFloat. Use the fact that we now know whether or not we cared about soft float to set the libcalls. Accordingly rename mipsSEUsesSoftFloat to abiUsesSoftFloat and propagate since it's no longer CPU specific. llvm-svn: 213335
* Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel2014-07-151-3/+4
| | | | | | | | | | | | | | | | | | | | | Refactoring; no functional changes intended Removed PostRAScheduler bits from subtargets (X86, ARM). Added PostRAScheduler bit to MCSchedModel class. This bit is set by a CPU's scheduling model (if it exists). Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses. Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!). Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling. Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values. Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86: a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget. b. MIPS overrides the CPU's postRA settings by enabling postRA for everything. c. PPC overrides the CPU's postRA settings by enabling postRA for everything. d. X86 is the only target that actually has postRA specified via sched model info. Differential Revision: http://reviews.llvm.org/D4217 llvm-svn: 213101
* [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI isSasa Stankovic2014-07-141-1/+2
| | | | | | | | | | | | | | | enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1) This prevents the upper 32-bits of a double precision value from being moved to the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure that the code generated executes correctly regardless of the current FPU mode. MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue to use dmtc1. Differential Revision: http://reviews.llvm.org/D4465 llvm-svn: 212930
* [mips] Added FPXX modeless calling convention.Zoran Jovanovic2014-07-101-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D4293 llvm-svn: 212726
* [mips] Add support for -modd-spreg/-mno-odd-spregDaniel Sanders2014-07-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When -mno-odd-spreg is in effect, 32-bit floating point values are not permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit floating point comparison results from being written to odd registers. This option has three purposes: * It allows support for certain MIPS implementations such as loongson-3a that do not allow the use of odd registers for single precision arithmetic. * When using -mfpxx, -mno-odd-spreg is the default and this allows us to statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1 instructions to/from odd registers are guaranteed not to appear for any reason. Once this has been established, the user can then re-enable -modd-spreg to regain the use of all 32 single-precision registers. * When using -mfp64 and -mno-odd-spreg together, an O32 extension named O32 FP64A is used as the ABI. This is intended to provide almost all functionality of an FR=1 processor but can also be executed on a FR=0 core with the assistance of a hardware compatibility mode which emulates FR=0 behaviour on an FR=1 processor. * Added '.module oddspreg' and '.module nooddspreg' each of which update the .MIPS.abiflags section appropriately * Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller doesn't have to remember to do it. * MipsABIFlags now calculates the flags1 and flags2 member on demand rather than trying to maintain them in the same format they will be emitted in. There is one portion of the -mfp64 and -mno-odd-spreg combination that is not implemented yet. Moves to/from odd-numbered double-precision registers must not use mtc1. I will fix this in a follow-up. Differential Revision: http://reviews.llvm.org/D4383 llvm-svn: 212717
* Mips.abiflags is a new implicitly generated section that will be present on ↵Vladimir Medic2014-07-081-0/+4
| | | | | | all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it. llvm-svn: 212519
* Move subtarget dependent features into the subtarget from the targetEric Christopher2014-07-031-1/+26
| | | | | | | machine. Includes a fix for a subtarget initialization for hard floating point on mips16. llvm-svn: 212240
* Move the data layout and selection dag info from the mips target machineEric Christopher2014-07-021-0/+7
| | | | | | down to the subtarget. llvm-svn: 212224
* Break out subtarget initialization that dependent variables need intoEric Christopher2014-07-021-0/+2
| | | | | | a separate function and clean up calling convention for helper function. llvm-svn: 212153
* Move MipsJITInfo to the subtarget rather than the target machine.Eric Christopher2014-07-021-0/+5
| | | | llvm-svn: 212151
* [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6Daniel Sanders2014-06-161-1/+4
| | | | | | | | | | | | | | | | | Summary: There is no change to the restrictions, just the result register is stored once in the encoding rather than twice. The rt field is zero in MIPS32r6/MIPS64r6. Depends on D4119 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4120 llvm-svn: 211019
* [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.Daniel Sanders2014-06-161-1/+1
| | | | | | | | | | | | | | | | | | | | | Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
* [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-06-121-5/+10
| | | | | | | | | | | | | | | | | | | | | | FP64 Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 llvm-svn: 210771
* [mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6Daniel Sanders2014-05-231-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
* [mips] Marked up instructions added in MIPS32r2 and tested that IAS for ↵Daniel Sanders2014-05-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
* [mips] Marked up instructions added in MIPS-V and tested that IAS for ↵Daniel Sanders2014-05-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | -mcpu=mips[1234] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-V that was available in MIPS32R2 Most of these instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. It happens because many of the MIPS V instructions have not been implemented. Depends on D3694 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3695 llvm-svn: 208546
* [mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64Daniel Sanders2014-05-121-4/+0
| | | | | | | | | | | | | | | | | | | | | Summary: DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no effect on the CodeGen tests since expansion of i64 prevented their use anyway. The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as well. This is not a functional change since DCLZ is still prohibited by being a MIPS64 instruction (MIPS16 is only compatible with MIPS32). No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3694 llvm-svn: 208544
* [mips] Fold FeatureSEInReg into FeatureMips32r2Daniel Sanders2014-05-121-4/+0
| | | | | | | | | | | | Summary: No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3693 llvm-svn: 208543
* [mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2Daniel Sanders2014-05-121-4/+0
| | | | | | | | | | | | | | | | | Summary: dsbh and dshd are not available on Mips32r2. No codegen test changes required since expansion of i64 prevented the use of these instructions anyway. Depends on D3690 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3692 llvm-svn: 208542
* [mips] Replace FeatureFPIdx with FeatureMips4_32r2Daniel Sanders2014-05-121-5/+5
| | | | | | | | | | | | | | | | | Summary: No functional change. The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions) Depends on D3677 Reviewers: rkotler, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3690 llvm-svn: 208541
* [mips] Marked up instructions added in MIPS-IV and tested that IAS for ↵Daniel Sanders2014-05-091-0/+4
| | | | | | | | | | | | | | | | | | | | | -mcpu=mips[123] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-IV that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. Depends on D3676 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3677 llvm-svn: 208414
* [mips] Remove unused CondMov feature bitDaniel Sanders2014-05-091-4/+0
| | | | | | | | | | | | | | | Summary: No functional change Depends on D3675 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3676 llvm-svn: 208410
* [mips] Marked up instructions added in MIPS-III and tested that IAS for ↵Daniel Sanders2014-05-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
* [mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6Daniel Sanders2014-05-091-2/+7
| | | | | | | | | | | | | | | | | | Summary: Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these processors. I've also included comments to describe removed and re-encoded instructions, along with placeholder def's for the new instructions but there are no functional changes to codegen at this point. Reviewers: jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3622 llvm-svn: 208399
* [mips] Marked up instructions added in MIPS-II and tested that IAS for ↵Daniel Sanders2014-05-081-0/+1
| | | | | | | | | | | | | | | | | | | -mcpu=mips1 does not accept them Summary: A small number of instructions are rejected with the wrong error message. These have been placed in a separate test for now. There seems to be some parsing quirk that triggers when these instructions are disabled. Depends on D3571 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3647 llvm-svn: 208305
* [mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-VDaniel Sanders2014-05-071-1/+2
| | | | | | | | | | | | | | | | | | | | Summary: These processors will only be available for the integrated assembler at first (CodeGen will emit a fatal error saying they are not implemented). The intention is to work through the existing instructions and correctly annotate the ISA they were added in so that we have a sufficiently good base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain instructions and I believe it is best to define ISA's using set-union's as far as possible rather than using set-subtraction. Reviewers: vmedic Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D3569 llvm-svn: 208221
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-3/+3
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
* [mips] Add initial support for NaN2008 in the back-end.Matheus Almeida2014-04-161-0/+4
| | | | | | | | | | | | This is so that EF_MIPS_NAN2008 is set if we are using IEEE 754-2008 NaN encoding (-mnan=2008). This patch also adds support for parsing '.nan legacy' and '.nan 2008' assembly directives. The handling of these directives should match GAS' behaviour i.e., the last directive in use sets the ELF header bit (EF_MIPS_NAN2008). Differential Revision: http://reviews.llvm.org/D3346 llvm-svn: 206396
* [mips] IndentationDaniel Sanders2014-04-161-4/+3
| | | | llvm-svn: 206389
* [mips] Add initial (experimental) MIPS-IV support.Daniel Sanders2014-04-031-4/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: Adds the 'mips4' processor and a simple test of the ELF e_flags. Patch by David Chisnall His work was sponsored by: DARPA, AFRL I made one small change to the testcase so that it uses mips64-unknown-linux instead of mips4-unknown-linux. This patch indirectly adds FeatureCondMov to FeatureMips64. This is ok because it's supposed to be there anyway and it turns out that FeatureCondMov is not a predicate of any instructions at the moment (this is a bug that hasn't been noticed because there are no targets without the conditional move instructions yet). CC: theraven Differential Revision: http://llvm-reviews.chandlerc.com/D3244 llvm-svn: 205530
* [MIPS] Add cpu octeon and some instructionsKai Nacke2014-03-201-0/+5
| | | | | | | | | | The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
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