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* [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal ↵Daniel Sanders2013-09-271-0/+5
| | | | | | error when using it in FR=0 mode. llvm-svn: 191498
* Fix a problem with dual mips16/mips32 mode. When the underlying processorReed Kotler2013-08-301-0/+3
| | | | | | | | | | | | | has hard float, when you compile the mips32 code you have to make sure that it knows to compile any mips32 routines as hard float. I need to clean up the way mips16 hard float is specified but I need to first think through all the details. Mips16 always has a form of soft float, the difference being whether the underlying hardware has floating point. So it's not really necessary to pass the -soft-float to llvm since soft-float is always true for mips16 by virtue of the fact that it will not register floating point registers. By using this fact, I can simplify the way this is all handled. llvm-svn: 189690
* Fix a subtle difference between running clang vs llc for mips16.Reed Kotler2013-08-161-0/+3
| | | | | | | | | | | | | | | | This regards how mips16 is viewed. It's not really a target type but there has always been a target for it in the td files. It's more properly -mcpu=mips32 -mattr=+mips16 . This is how clang treats it but we have always had the -mcpu=mips16 which I probably should delete now but it will require updating all the .ll test cases for mips16. In this case it changed how we decide if we have a count bits instruction and whether instruction lowering should then expand ctlz. Now that we have dual mode compilation, -mattr=+mips16 really just indicates the inital processor mode that we are compiling for. (It is also possible to have -mcpu=64 -mattr=+mips16 but as far as I know, nobody has even built such a processor, though there is an architecture manual for this). llvm-svn: 188586
* [Mips][msa] Added initial MSA support.Jack Carter2013-08-131-1/+1
| | | | | | | | | | | | * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-1/+1
| | | | llvm-svn: 187832
* Checkin in of first of several patches to finish implementation ofReed Kotler2013-05-101-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
* This is for an experimental option -mips-os16. The idea is to compile allReed Kotler2013-04-101-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mips32 code as Mips16 unless it can't be compiled as Mips 16. For now this would happen as long as floating point instructions are not needed. Probably it would also make sense to compile as mips32 if atomic operations are needed too. There may be other cases too. A module pass prescans the IR and adds the mips16 or nomips16 attribute to functions depending on the functions needs. Mips 16 mode can result in a 40% code compression by utililizing 16 bit encoding of many instructions. The hope is for this to replace the traditional gcc way of dealing with Mips16 code using floating point which involves essentially using soft float but with a library implemented using mips32 floating point. This gcc method also requires creating stubs so that Mips32 code can interact with these Mips 16 functions that have floating point needs. My conjecture is that in reality this traditional gcc method would never win over this new method. I will be implementing the traditional gcc method also. Some of it is already done but I needed to do the stubs to finish the work and those required this mips16/32 mixed mode capability. I have more ideas for to make this new method much better and I think the old method will just live in llvm for anyone that needs the backward compatibility but I don't for what reason that would be needed. llvm-svn: 179185
* This patch enables llvm to switch between compiling for mips32/mips64 Reed Kotler2013-04-091-2/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and mips16 on a per function basis. Because this patch is somewhat involved I have provide an overview of the key pieces of it. The patch is written so as to not change the behavior of the non mixed mode. We have tested this a lot but it is something new to switch subtargets so we don't want any chance of regression in the mainline compiler until we have more confidence in this. Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1. For that reason there are derived versions of the register info, frame info, instruction info and instruction selection classes. Now we register three separate passes for instruction selection. One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and MipsSEISelDAGToDAG.cpp). When the ModuleISel pass runs, it determines if there is a need to switch subtargets and if so, the owning pointers in MipsTargetMachine are appropriately changed. When 16Isel or SEIsel is run, they will return immediately without doing any work if the current subtarget mode does not apply to them. In addition, MipsAsmPrinter needs to be reset on a function basis. The pass BasicTargetTransformInfo is substituted with a null pass since the pass is immutable and really needs to be a function pass for it to be used with changing subtargets. This will be fixed in a follow on patch. llvm-svn: 179118
* [mips] Remove android calling convention.Akira Hatanaka2013-03-051-1/+1
| | | | | | | This calling convention was added just to handle functions which return vector of floats. The fix committed in r165585 solves the problem. llvm-svn: 176530
* This patch that sets the Mips ELF header flag for Jack Carter2013-02-051-1/+2
| | | | | | | | MicroMips architectures. Contributer: Zoran Jovanovic llvm-svn: 174360
* This patch implements runtime Mips specificJack Carter2013-01-301-2/+2
| | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter llvm-svn: 173884
* [mips] Delete unused sub-target features.Akira Hatanaka2012-12-071-2/+2
| | | | llvm-svn: 169578
* [mips] Add predicate HasFPIdx for floating-point indexed load instructionAkira Hatanaka2012-11-151-2/+2
| | | | | | support and use it in place of HasMips32r2Or64. llvm-svn: 168089
* Initialize boolean variables in MipsSubtarget's constructor.Akira Hatanaka2012-09-251-1/+2
| | | | llvm-svn: 164642
* Add register Mips::GP to the list of reserved registers if target is bare-metalAkira Hatanaka2012-08-221-1/+5
| | | | | | | | to prevent it from being clobbered. mips uses $gp to access small data section. This bug was originally reported by Carl Norum. llvm-svn: 162340
* Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka2012-06-141-2/+2
| | | | llvm-svn: 158471
* This patch adds the register class for MIPS16 as well as the ability forAkira Hatanaka2012-05-161-1/+1
| | | | | | | | | | | | | | | llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. llvm-svn: 156958
* Temporarily disable anti-dependence breaking for Mips until bug 12829 isAkira Hatanaka2012-05-151-1/+1
| | | | | | resolved. llvm-svn: 156801
* Turn off post-RA scheduler by default.Akira Hatanaka2012-03-281-1/+1
| | | | llvm-svn: 153557
* Turn on post register allocation scheduler.Akira Hatanaka2012-03-281-0/+12
| | | | llvm-svn: 153554
* remove blanks, and some code formatJia Liu2012-02-281-2/+2
| | | | llvm-svn: 151625
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-171-1/+1
| | | | llvm-svn: 150805
* Unweaken vtables as per ↵David Blaikie2011-12-201-0/+2
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Change names for MIPS "generic" processors defined in Mips.td to match what GNUAkira Hatanaka2011-11-291-1/+1
| | | | | | | | | | tools use. Patch by Simon Atanasyan. "mips32r1" => "mips32" "4ke" => mips32r2" "mips64r1" => "mips64" llvm-svn: 145451
* Undo a change made in r140254.Akira Hatanaka2011-09-211-4/+4
| | | | | | MipsArchVersion needs to be initialized to Mips32. llvm-svn: 140261
* MipsArchVersion does not need to be in the initialization list and MipsABIAkira Hatanaka2011-09-211-1/+1
| | | | | | should be initialized to UnknownABI. llvm-svn: 140254
* Set ABI if it hasn't been set on the command line.Akira Hatanaka2011-09-211-0/+9
| | | | | | Check if architecture & ABI combination is valid. llvm-svn: 140230
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-091-1/+1
| | | | llvm-svn: 139405
* Drop support for Allegrex. Allegrex implements a variant of Mips2.Akira Hatanaka2011-09-091-16/+0
| | | | llvm-svn: 139383
* Change default target architecture from Mips1 to Mips32r1 in preparation forAkira Hatanaka2011-09-091-2/+1
| | | | | | | | | removing support for Mips1 and Mips2. This change and the ones that follow have been discussed with and approved by Bruno. llvm-svn: 139344
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-14/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-1/+1
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-091-0/+13
| | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-1/+2
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-071-2/+2
| | | | llvm-svn: 134606
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134281
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-011-1/+1
| | | | llvm-svn: 134259
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-011-0/+9
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-301-4/+6
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka2011-04-151-3/+3
| | | | | | in functionality. llvm-svn: 129612
* Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka2011-04-151-3/+3
| | | | | | change in functionality. llvm-svn: 129606
* Remove (hopefully) all trailing whitespaces from the mips backend. Patch by ↵Bruno Cardoso Lopes2011-03-041-2/+2
| | | | | | Hatanaka, Akira llvm-svn: 127003
* reintroduce support for Mips "small" section handling. This is Chris Lattner2009-08-131-9/+0
| | | | | | | implemented somewhat differently than before, but it should have the same functionality and the previous testcase passes again. llvm-svn: 78900
* Restore some "small section" support code, reverting my patch from r76936.Chris Lattner2009-08-131-0/+8
| | | | llvm-svn: 78894
* Remove -disable-mips-abicall and -enable-mips-absolute-call command-line Eli Friedman2009-08-031-21/+5
| | | | | | | | | | | | | options, which don't appear to be useful. -enable-mips-absolute-call is completely unused (and unless I'm mistaken, is supposed to have the same effect that -relocation-model=dynamic-no-pic should have), and -disable-mips-abicall appears to be effectively a synonym for -relocation-model=static. Adjust the few users of hasABICall to checks which seem more appropriate. Update MipsSubtarget, MipsTargetMachine, and MipselTargetMachine to synchronize with recent changes. llvm-svn: 77938
* Normalize Subtarget constructors to take a target triple string instead ofDaniel Dunbar2009-08-021-3/+1
| | | | | | | | | | Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. llvm-svn: 77918
* remove more remnants of small section support.Chris Lattner2009-07-241-7/+0
| | | | llvm-svn: 76936
* Added support for fround, fextend and FP_TO_SINTBruno Cardoso Lopes2009-05-271-0/+1
| | | | llvm-svn: 72483
* Fixed Bug 2751Bruno Cardoso Lopes2008-09-151-3/+3
| | | | | | | | | | | http://llvm.org/bugs/show_bug.cgi?id=2751 Abicall was enabled even when static code model was provided in the command line. The correct behavior is to disable abicall when static is specified. llvm-svn: 56228
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