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path: root/llvm/lib/Target/Mips/MipsScheduleP5600.td
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* [Mips] Add support for min/max/umin/umax atomicsMirko Brkusanin2019-12-121-1/+2
| | | | | | | | In order to properly implement these atomic we need one register more than other binary atomics. It is used for storing result from comparing values in addition to the one that is used for actual result of operation. https://reviews.llvm.org/D71028
* [mips] Implement Octeon+ `saa` and `saad` instructionsSimon Atanasyan2019-11-071-1/+2
| | | | | | | | | | | | | | | `saa` and `saad` are 32-bit and 64-bit store atomic add instructions. memory[base] = memory[base] + rt These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+". Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP` ISA extension flag support. Differential Revision: https://reviews.llvm.org/D69849
* [mips] Mark P5600 scheduling model as completeSimon Atanasyan2019-07-021-1/+1
| | | | llvm-svn: 364902
* [mips] Add missing schedinfo for FPU load/store/conv instructionsSimon Atanasyan2019-07-021-4/+10
| | | | llvm-svn: 364900
* [mips] Map SNOP, NOP to the P5600Nop scheduler resourceSimon Atanasyan2019-07-021-2/+8
| | | | llvm-svn: 364899
* [mips] Add virtualization ASE to P5600 scheduling definitionsSimon Atanasyan2019-07-011-0/+5
| | | | llvm-svn: 364849
* [mips] Add missing schedinfo for MSA and ASE instructionsSimon Atanasyan2019-07-011-0/+6
| | | | llvm-svn: 364757
* [mips] Add missing schedinfo for atomic instructionsSimon Atanasyan2019-07-011-0/+16
| | | | llvm-svn: 364756
* [mips] Add new items to the list of features unsupported by P5600Simon Atanasyan2019-06-271-3/+3
| | | | llvm-svn: 364539
* [mips] Add PTR_64 and GPR_64 predicates to some MIPS 64-bit instructionsSimon Atanasyan2019-06-181-1/+2
| | | | | | | | | | | | | | | Add `IsGP64bit` and `IsPTR64bit` to the list of `UnsupportedFeatures` of the P5600 scheduling definitions. Also mark some MIPS 64-bit instructions by PTR_64 and GPR_64 predicates. This reduces number of "No schedule information for" and "lacks information for" errors in case of marking this scheduler model as complete. This patch is one of a series of patches. The goal is to make P5600 scheduler model complete and turn on the `CompleteModel` flag. Differential Revision: https://reviews.llvm.org/D63237 llvm-svn: 363702
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [mips] Update the P5600 scheduler model not to use instruction itineraries.Simon Atanasyan2018-07-111-63/+93
| | | | | | | | | | | | | | | This mostly brings the P5600 scheduler model to a mostly complete status. There are a number of instructions which trigger the `error:'MipsP5600Model' lacks information for` error. These are certain codegen only instructions relating to MIPS64 which can be addressed by using the correct predicates for them. That will be done in a full-up patch. Patch by Simon Dardis. Differential revision: https://reviews.llvm.org/D45245 llvm-svn: 336802
* [SchedModel] Complete models shouldn't match against itineraries when they ↵Simon Pilgrim2018-04-051-1/+1
| | | | | | | | | | | | don't use them (PR35639) For schedule models that don't use itineraries, checkCompleteness still checks that an instruction has a matching itinerary instead of skipping and going straight to matching the InstRWs. That doesn't seem to match what happens in TargetSchedule.cpp This patch causes problems for a number of models that had been incorrectly flagged as complete. Differential Revision: https://reviews.llvm.org/D43235 llvm-svn: 329280
* [Mips] Remove duplicate lines from MipsScheduleP5600.td and enable ↵Craig Topper2018-03-181-21/+0
| | | | | | | | FullInstRWOverlapCheck. This fixes the errors found by the new check added in r327808. llvm-svn: 327813
* [TableGen] When trying to reuse a scheduler class for instructions from an ↵Craig Topper2018-03-181-0/+2
| | | | | | | | | | | | InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check. So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag. A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found. llvm-svn: 327808
* [mips] Begin reworking instruction predicates for ISAs/encodings (1/N)Simon Dardis2018-02-281-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS backend has inconsistent usage of instruction predicates for assembly and code generation. The issue arises from supporting three encodings, two (MIPS and microMIPS) of which have a near 1:1 instruction mapping across ISA revisions and a third encoding with a more restricted set of instructions (MIPS16e). To enforce consistent usage, each of the ISA_* adjectives has (or will have) the relevant encoding attached to it along the relevant ISA revision where the instruction is defined. Each instruction, pattern or alias will then have the correct ISA adjective attached to it, and the base instruction description classes will have any predicates relating to ISA encoding or revision removed. Pseudo instructions will also be guarded for the encoding or ABI that they are supported in. Finally, the hasStandardEncoding() / inMicroMipsMode() / inMips16Mode() methods of MipsSubtarget will be changed such that only one can be true at any one time. The result of this is that code generation and assembly will produce the correct encoding up front, while code generated from pseudo instructions and other inserted sequences of instructions will be able to rely on the mapping tables to produce the correct encoding. This should fix numerous bugs where the result 'happens' to be correct but has edge cases where microMIPS and MIPS have subtle differences (e.g. microMIPSR6 using 'j', 'jal' instructions.) This patch starts the process by changing most of the ISA adjectives to make use of the EncodingPredicate member of PredicateControl. Follow on patches will annotate instructions with their correct ISA adjective and eliminate the usage of "let Predicates = [..]", "let AdditionalPredicates = [..]" and "isCodeGenOnly = 1" in the cases where it was used to control instruction availability. Contributions from Nitesh Jain. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41434 llvm-svn: 326322
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-111-2/+2
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* [mips][mt][3/7] Add IAS support for emt, dmt instructions.Simon Dardis2017-07-121-1/+1
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35250 llvm-svn: 307774
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-051-0/+3
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-051-3/+0
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [mips] Add rsqrt, recip for MIPSSimon Dardis2016-09-271-0/+3
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
* [mips] Update the P5600 scheduler for isComplete = 1Simon Dardis2016-08-021-30/+221
| | | | | | | | | | | These changes update the schedule model for the P5600 and includes the rest of the MSA and MIPS32R5 instruction sets. Reviewers: dsanders, vkalintris Differential Revision: https://reviews.llvm.org/D21835 llvm-svn: 277441
* TableGen: Check scheduling models for completenessMatthias Braun2016-03-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | TableGen checks at compiletime that for scheduling models with "CompleteModel = 1" one of the following holds: - Is marked with the hasNoSchedulingInfo flag - The instruction is a subclass of Sched - There are InstRW definitions in the scheduling model Typical steps necessary to complete a model: - Ensure all pseudo instructions that are expanded before machine scheduling (usually everything handled with EmitYYY() functions in XXXTargetLowering). - If a CPU does not support some instructions mark the corresponding resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }". - Add missing scheduling information. Differential Revision: http://reviews.llvm.org/D17747 llvm-svn: 262384
* [mips][p5600] Added P5600 processor and initial scheduler.Daniel Sanders2015-09-281-0/+392
Summary: The P5600 is an out-of-order, superscalar implementation of the MIPS32R5 architecture. The scheduler has a few missing details (see the 'Tricky Instructions' section and some quirks of the P5600 are deliberately omitted due to implementation difficulty and low chance of significant benefit (e.g. the predicate on P5600WriteEitherALU). However, testing on SingleSource is showing significant performance benefits on some apps (seven in the 10-30% range) and only one significant regression (12%) when -pre-RA-sched=linearize is given. Without -pre-RA-sched=linearize the results are more variable. Some do even better (up to 55% improvement) but increased numbers of copies are slowing others down (up to 12%). Overall, the scheduler as it currently stands is a 2.4% win with -pre-RA-sched=linearize and a 2.7% win without -pre-RA-sched=linearize. I'm sure we can improve on this further. For completeness, the FPGA this was tested on shows some failures with and without the P5600 scheduler. These appear to be scheduling related since the two test runs have fairly different sets of failing tests even after accounting for other factors (e.g. spurious connection failures) however it's not P5600 specific since we also get some for the generic scheduler. Reviewers: vkalintiris Subscribers: mpf, llvm-commits, atrick, vkalintiris Differential Revision: http://reviews.llvm.org/D12193 llvm-svn: 248725
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