summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips/MipsScheduleGeneric.td
Commit message (Collapse)AuthorAgeFilesLines
* [Mips] Add support for min/max/umin/umax atomicsMirko Brkusanin2019-12-121-1/+2
| | | | | | | | In order to properly implement these atomic we need one register more than other binary atomics. It is used for storing result from comparing values in addition to the one that is used for actual result of operation. https://reviews.llvm.org/D71028
* [mips] Implement Octeon+ `saa` and `saad` instructionsSimon Atanasyan2019-11-071-2/+7
| | | | | | | | | | | | | | | `saa` and `saad` are 32-bit and 64-bit store atomic add instructions. memory[base] = memory[base] + rt These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+". Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP` ISA extension flag support. Differential Revision: https://reviews.llvm.org/D69849
* [mips] Fix JmpLink to texternalsym and tglobaladdr on mcroMIPS R6Simon Atanasyan2019-07-121-1/+1
| | | | | | | | | | | | | | | | There is not match for the `MipsJmpLink texternalsym` and `MipsJmpLink tglobaladdr` patterns for microMIPS R6. As a result LLVM incorrectly selects the `JALRC16` compact 2-byte instruction which takes a target instruction address from a register only and assign `R_MIPS_32` relocation for this instruction. This relocation completely overwrites `JALRC16` and nearby instructions. This patch adds missed matching patterns, selects `BALC` instruction and assign a correct `R_MICROMIPS_PC26_S1` relocation. Differential Revision: https://reviews.llvm.org/D64552 llvm-svn: 365870
* [mips] Mark general scheduling model as completeSimon Atanasyan2019-07-031-2/+2
| | | | llvm-svn: 365034
* [mips] Add missing atomic instructions to general scheduling definitionsSimon Atanasyan2019-07-031-0/+16
| | | | llvm-svn: 365033
* [mips] Add missing microMIPS instructions to general scheduling definitionsSimon Atanasyan2019-07-031-12/+25
| | | | llvm-svn: 365032
* [mips] Add SIGRIE,GINVI,GINVT to general scheduling definitionsSimon Atanasyan2019-07-031-2/+5
| | | | llvm-svn: 365023
* [mips] Add missing mips16 instructions to general scheduling definitionsSimon Atanasyan2019-07-031-0/+3
| | | | llvm-svn: 365022
* [mips] Add missing MSA and ASE instructions to general scheduling definitionsSimon Atanasyan2019-07-031-0/+33
| | | | llvm-svn: 365021
* [mips] Replace some itineraries by instructions in the general scheduling ↵Simon Atanasyan2019-07-031-187/+668
| | | | | | definitions llvm-svn: 365020
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [mips] Support sigrie instructionSimon Atanasyan2018-11-061-1/+1
| | | | | | | | | The `sigrie` instruction signals a Reserved Instruction Exception. This patch adds support for assembling / disassembling the instruction. Differential Revision: http://reviews.llvm.org/D53861 llvm-svn: 346230
* [MIPS] Fix DIV/DIVU scheduling classes.Clement Courbet2018-05-021-2/+2
| | | | | | https://reviews.llvm.org/D46356. llvm-svn: 331354
* [SchedModel] Complete models shouldn't match against itineraries when they ↵Simon Pilgrim2018-04-051-1/+1
| | | | | | | | | | | | don't use them (PR35639) For schedule models that don't use itineraries, checkCompleteness still checks that an instruction has a matching itinerary instead of skipping and going straight to matching the InstRWs. That doesn't seem to match what happens in TargetSchedule.cpp This patch causes problems for a number of models that had been incorrectly flagged as complete. Differential Revision: https://reviews.llvm.org/D43235 llvm-svn: 329280
* [TableGen] When trying to reuse a scheduler class for instructions from an ↵Craig Topper2018-03-181-0/+3
| | | | | | | | | | | | InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check. So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag. A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found. llvm-svn: 327808
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-11-141-1/+3
| | | | | | | | | | | | | | | | | | | | This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 318207
* [mips] Add movep for microMIPS32R6 and fix microMIPS32r3 versionSimon Dardis2017-11-061-0/+1
| | | | | | | | | | | | | | | | | | | Previously, the 'movep' instruction was defined for microMIPS32r3 and shared that definition with microMIPS32R6. 'movep' was re-encoded for microMIPS32r6, so this patch provides the correct encoding. Secondly, correct the encoding of the 'rs' and 'rt' operands which have an instruction specific encoding for the registers those operands accept. Finally, correct the decoding of the 'dst_regs' operand which was extracting the relevant field from the instruction, but was actually extracting the field from the alreadly extracted field. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39495 llvm-svn: 317475
* Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-08-141-3/+1
| | | | | | | This reverts r310834. It didn't pacify the buildbot, FileCheck is still crashing. llvm-svn: 310854
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-08-141-1/+3
| | | | | | | | | | | | | | | | | | | | This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 310834
* [mips][mt][5/7] Add support for fork and yield instructions.Simon Dardis2017-07-121-1/+7
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35252 llvm-svn: 307808
* [mips][mt][4/7] Add IAS support for dvpe, evpe instructions.Simon Dardis2017-07-121-1/+1
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35251 llvm-svn: 307793
* [mips][mt][3/7] Add IAS support for emt, dmt instructions.Simon Dardis2017-07-121-0/+6
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35250 llvm-svn: 307774
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-051-0/+4
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-051-4/+0
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [mips] Add rsqrt, recip for MIPSSimon Dardis2016-09-271-0/+4
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
* [mips] Include missed file from previous commitSimon Dardis2016-09-011-0/+1044
llvm-svn: 280377
OpenPOWER on IntegriCloud