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* [mips] Disable the selection of mixed microMIPS/MIPS codeSimon Atanasyan2018-09-031-4/+8
| | | | | | | | | | | | | This patch modifies hasStandardEncoding() / inMicroMipsMode() / inMips16Mode() methods of the MipsSubtarget class so only one can be true at any one time. That prevents the selection of microMIPS and MIPS instructions and patterns that are defined in TableGen files at the same time. A few new patterns and instruction definitions hae been added to keep test cases passed. Differential revision: https://reviews.llvm.org/D51483 llvm-svn: 341338
* Make TargetInstrInfo::isCopyInstr return true for regular COPY-instructionsAlexander Ivchenko2018-08-301-3/+3
| | | | | | | | | | | ..Move all target-dependent checks into new isCopyInstrImpl method. This change allows us to treat MoveReg-type instructions and generic COPY instruction in the same way Differential Revision: https://reviews.llvm.org/D49913 llvm-svn: 341072
* [mips] Fix microMIPS unconditional branch offset handlingSimon Atanasyan2018-08-291-2/+7
| | | | | | | | | | | | | | MipsSEInstrInfo class defines for internal purpose unconditional branches as Mips::B nad Mips:J even in case of microMIPS code generation. Under some conditions that leads to the bug - for rather long branch which fits to Mips jump instruction offset size, but does not fit to microMIPS jump offset size, we generate 'short' branch and later show an error 'out of range PC16 fixup' after check in the isBranchOffsetInRange routine. Differential revision: https://reviews.llvm.org/D50615 llvm-svn: 340932
* [mips] Involves microMIPS's jump in the analyzable branch setSimon Atanasyan2018-08-291-1/+1
| | | | | | | | | Involves microMIPS's jump in the analyzable branch set to reduce some code patterns. Differential revision: https://reviews.llvm.org/D50613 llvm-svn: 340931
* [Mips] Silencing warnings in instruction info (NFC)Petar Jovanovic2018-06-071-12/+18
| | | | | | | | | | | isORCopyInst and isReadOrWriteToDSPReg functions were producing warning that some statements my fall through. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D47876 llvm-svn: 334194
* Change TII isCopyInstr way of returning arguments(NFC)Petar Jovanovic2018-06-061-9/+10
| | | | | | | | | | | Make TII isCopyInstr() return MachineOperands through pointer to pointer instead via reference. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D47364 llvm-svn: 334105
* Silence warnings introduced with r333093Petar Jovanovic2018-05-231-1/+1
| | | | | | | | r333093 introduced several warnings (-Wlogical-not-parentheses, -Wbool-compare). Adding parentheses in MipsSEInstrInfo::isCopyInstr() to silence it. llvm-svn: 333097
* [X86][MIPS][ARM] New machine instruction property 'isMoveReg'Petar Jovanovic2018-05-231-0/+56
| | | | | | | | | | | | | This property is needed in order to follow values movement between registers. This property is used in TII to implement method that returns true if simple copy like instruction is recognized, along with source and destination machine operands. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D45204 llvm-svn: 333093
* [mips] Add support for isBranchOffsetInRange and use it for MipsLongBranchSimon Dardis2018-05-161-10/+40
| | | | | | | | | | | | Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
* [mips] Analyze and provide selection patterns microMIPSR6 branchesSimon Dardis2018-04-271-1/+15
| | | | | | | | | | | These branches were previously unanalyzable and unselectable. Add them and recognize how to generate their inverses. Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46113 llvm-svn: 331050
* [mips] Define certain instructions in microMIPS32r3Stefan Maksimovic2018-02-081-9/+18
| | | | | | | | | | | | | | | | | | | | Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-4/+4
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* [mips] Correct microMIP's jump and add unconditional branch pseudoSimon Dardis2017-11-091-11/+11
| | | | | | | | | | | | | | Correct the definition of 'j' as being unavailable for microMIPS32R6 and provide the 'b' assembly idiom for codegen purposes for microMIPS32r3. Provide the necessary 'br' pattern for microMIPS32R6 as it now longer incorrectly uses the 'j' instruction. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39741 llvm-svn: 317801
* [mips] Enable spilling and reloading of the dsp register set.Simon Dardis2017-10-031-0/+4
| | | | | | | | | | | The dsp register class is an alias of the gpr register class, so we have to define instructions for spilling and reloading. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D38038 llvm-svn: 314798
* [Mips] Fix for BBIT octeon instructionStrahinja Petrovic2017-08-011-1/+7
| | | | | | | | | | | This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction. Differential Revision: https://reviews.llvm.org/D35359 llvm-svn: 309679
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-8/+14
| | | | | | Differential Revision: https://reviews.llvm.org/D31937 llvm-svn: 301234
* Revert r301231: Accidentally committed stale filesKrzysztof Parzyszek2017-04-241-8/+8
| | | | | | I forgot to commit local changes before commit. llvm-svn: 301232
* Move value type list from TargetRegisterClass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-8/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D31937 llvm-svn: 301231
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-2/+2
| | | | | | | | | | | | | | | 1. RegisterClass::getSize() is split into two functions: - TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const; - TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const; 2. RegisterClass::getAlignment() is replaced by: - TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const; This will allow making those values depend on subtarget features in the future. Differential Revision: https://reviews.llvm.org/D31783 llvm-svn: 301221
* [mips] Fix return loweringSimon Dardis2017-03-091-3/+12
| | | | | | | | | | | | | Fix a machine verifier issue where a instruction was using a invalid register. The return pseudo is expanded and has the return address register added to it. The return register may have been spuriously mark as killed earlier. This partially resolves PR/27458 Thanks to Quentin Colombet for reporting the issue! llvm-svn: 297372
* Revert "[mips] Fix c.<cc>.<fmt> instruction definition."Simon Dardis2016-09-091-34/+0
| | | | | | | This reverts commit r281022. Mips buildbot broke, due to unhandled register class FCC. llvm-svn: 281033
* [mips] Fix c.<cc>.<fmt> instruction definition.Simon Dardis2016-09-091-0/+34
| | | | | | | | | | | | | | | As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
* [mips] MIPS64R6 compact branch supportSimon Dardis2016-07-261-2/+18
| | | | | | | | | | | | | MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that map to the same instruction, extend compact branch support for the corresponding 64bit branches. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D20164 llvm-svn: 276739
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-07-221-10/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D19906 llvm-svn: 276397
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* Convert more cases to isPositionIndependent(). NFC.Rafael Espindola2016-06-281-3/+2
| | | | llvm-svn: 274021
* [mips] Optimize stack pointer adjustments.Simon Dardis2016-06-141-4/+12
| | | | | | | | | | | | | | | | | | | | | Instead of always using addu to adjust the stack pointer when the size out is of the range of an addiu instruction, use subu so that a smaller constant can be generated. This can give savings of ~3 instructions whenever a function has a a stack frame whose size is out of range of an addiu instruction. This change may break some naive stack unwinders. Partially resolves PR/26291. Thanks to David Chisnall for reporting the issue. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D21321 llvm-svn: 272666
* [mips][msa] copyPhysReg() should not set RegState::Define on result of CTCMSA.Daniel Sanders2016-06-141-2/+5
| | | | | | | | | | | | | | Summary: The machine verifier reports 'Explicit operand marked as def' when it is manually specified even though it agrees with the operand info. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21065 llvm-svn: 272646
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-7/+7
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* [mips] Fix a small typo that would leave BLTZC out of getAnalyzableBrOpc().'Vasileios Kalintiris2016-04-221-1/+1
| | | | llvm-svn: 267149
* [NFC] Header cleanupMehdi Amini2016-04-181-2/+1
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [mips] MIPS32R6 compact branch supportDaniel Sanders2016-03-141-2/+14
| | | | | | | | | | | | | | | | | | | | | | | Summary: MIPSR6 introduces a class of branches called compact branches. Unlike the traditional MIPS branches which have a delay slot, compact branches do not have a delay slot. The instruction following the compact branch is only executed if the branch is not taken and must not be a branch. It works by generating compact branches for MIPS32R6 when the delay slot filler cannot fill a delay slot. Then, inspecting the generated code for forbidden slot hazards (a compact branch with an adjacent branch or other CTI) and inserting nops to clear this hazard. Patch by Simon Dardis. Reviewers: vkalintiris, dsanders Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16353 llvm-svn: 263444
* [mips] Remove redundant inclusions of MipsAnalyzeImmediate.hDaniel Sanders2016-02-031-0/+1
| | | | llvm-svn: 259655
* [mips] Correct operand order in DSP's mthi/mtloDaniel Sanders2016-01-121-2/+3
| | | | | | | | | | | | Summary: The result register is the second operand as per the other mt* instructions. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D15993 llvm-svn: 257478
* [mips] Interrupt attribute support for mips32r2+.Vasileios Kalintiris2015-10-261-2/+76
| | | | | | | | | | | | | | | | | | | Summary: This patch adds support for using the "interrupt" attribute on Mips for interrupt handling functions. At this time only mips32r2+ with the o32 ABI with the static relocation model is supported. Unsupported configurations will be rejected Patch by Simon Dardis (+ clang-format & some trivial changes to follow the LLVM coding standards by me). Reviewers: mpf, dsanders Subscribers: dsanders, vkalintiris, llvm-commits Differential Revision: http://reviews.llvm.org/D10768 llvm-svn: 251286
* [mips] Remove incorrect DebugLoc entries from prologuePetar Jovanovic2015-08-281-2/+1
| | | | | | | | | | This has been causing the prologue_end to be incorrectly positioned. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D11293 llvm-svn: 246309
* [mips] Remap move as or.Vasileios Kalintiris2015-08-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 llvm-svn: 244579
* [mips] Move ABI-dependent register selections to MipsABIInfo. NFC.Daniel Sanders2015-04-171-4/+5
| | | | | | | | | | | | | | | | | | | | | Summary: For example, a common idiom was 'isN64 ? Mips::SP_64 : Mips::SP'. This has been moved to MipsABIInfo and replaced with 'ABI.GetStackPtr()'. There are others that should also be moved. This patch sticks to the ones that are obviously non-functional. The others have minor mistakes that need fixing at the same time, mostly involving checks for 64-bit GPR's instead of checks for 64-bit pointers. Reviewers: tomatabacu Reviewed By: tomatabacu Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8972 llvm-svn: 235173
* [mips] Make sure that we don't adjust the stack pointer by zero amount.Vasileios Kalintiris2015-04-021-0/+3
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8638 llvm-svn: 233904
* Remove the need to cache the subtarget in the Mips TargetRegisterInfoEric Christopher2015-03-121-1/+1
| | | | | | classes. llvm-svn: 232012
* Fix a couple of odd formatting issues.Eric Christopher2015-01-081-6/+4
| | | | llvm-svn: 225457
* This routine is in InstrInfo, there's no need to access it again.Eric Christopher2015-01-081-8/+3
| | | | llvm-svn: 225456
* Remove dead variable.Eric Christopher2015-01-061-1/+1
| | | | llvm-svn: 225233
* [mips][microMIPS] This patch implements functionality in MIPS delay slotJozef Kolek2014-11-211-1/+3
| | | | | | | | | | | filler such as if delay slot filler have to put NOP instruction into the delay slot of microMIPS BEQ or BNE instruction which uses the register $0, then instead of emitting NOP this instruction is replaced by the corresponding microMIPS compact branch instruction, i.e. BEQZC or BNEZC. Differential Revision: http://reviews.llvm.org/D3566 llvm-svn: 222580
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-3/+6
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Make InstrInfo depend only upon the Subtarget getting passed inEric Christopher2014-07-181-24/+22
| | | | | | rather than the TargetMachine. llvm-svn: 213425
* [mips] For the FP64A ABI, odd-numbered double-precision moves must not use ↵Daniel Sanders2014-07-141-3/+21
| | | | | | | | | | | | | | | | | | | | | mtc1/mfc1. Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers to the upper 32-bits of the corresponding even register. In effect, simulating FR=0 mode when FR=0 mode is not available. Unfortunately, we have to make the decision to avoid mfc1/mtc1 before register allocation so we currently do this for even registers too. FPXX has a similar requirement on 32-bit architectures that lack mfhc1/mthc1 so this patch also handles the affected moves from the FPU for FPXX too. Moves to the FPU were supported by an earlier commit. Differential Revision: http://reviews.llvm.org/D4484 llvm-svn: 212938
* [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-07-141-4/+5
| | | | | | | | | | | | | | FP64 moves Summary: This is similar to r210771 which did the same thing for MTHC1. Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the wrong definitions. Differential Revision: http://reviews.llvm.org/D4483 llvm-svn: 212936
* [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI isSasa Stankovic2014-07-141-10/+9
| | | | | | | | | | | | | | | enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1) This prevents the upper 32-bits of a double precision value from being moved to the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure that the code generated executes correctly regardless of the current FPU mode. MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue to use dmtc1. Differential Revision: http://reviews.llvm.org/D4465 llvm-svn: 212930
* [mips][mips64r6] Use JALR for returns instead of JR (which is not available ↵Daniel Sanders2014-07-091-11/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on MIPS32r6/MIPS64r6) Summary: RET, and RET_MM have been replaced by a pseudo named PseudoReturn. In addition a version with a 64-bit GPR named PseudoReturn64 has been added. Instruction selection for a return matches RetRA, which is expanded post register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter, this PseudoReturn/PseudoReturn64 are emitted as: - (JALR64 $zero, $rs) on MIPS64r6 - (JALR $zero, $rs) on MIPS32r6 - (JR_MM $rs) on microMIPS - (JR $rs) otherwise On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid development and review (specifically, to ensure all cases of jr are updated), these aliases are temporarily named 'r6.jr' instead of 'jr'. A follow up patch will change them back to the correct mnemonic. Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect jump, and removed it from its definition of a call. Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's doesn't appear to account for any MIPS64-specifics. The return instruction created as part of eh_return expansion is now expanded using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6 ('jalr $zero, $rs'). Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in expandEhReturn(). Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4268 llvm-svn: 212604
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