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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-04-24 19:43:45 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-04-24 19:43:45 +0000 |
| commit | c0197066d786db4d04baadacfb3a88244e0026f4 (patch) | |
| tree | ea22ebe63d7242d8cd4be2bc5406652378d72bd2 /llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | |
| parent | 0774ea267a2cae366a33434e2a0536db6428c3dc (diff) | |
| download | bcm5719-llvm-c0197066d786db4d04baadacfb3a88244e0026f4.tar.gz bcm5719-llvm-c0197066d786db4d04baadacfb3a88244e0026f4.zip | |
Move value type list from TargetRegisterClass to TargetRegisterInfo
Differential Revision: https://reviews.llvm.org/D31937
llvm-svn: 301231
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSEInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index 6ce3f88507c..2bc371c5596 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -207,13 +207,13 @@ storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Opc = Mips::SDC1; else if (Mips::FGR64RegClass.hasSubClassEq(RC)) Opc = Mips::SDC164; - else if (RC->hasType(MVT::v16i8)) + else if (TRI->hasType(*RC, MVT::v16i8)) Opc = Mips::ST_B; - else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16)) + else if (TRI->hasType(*RC, MVT::v8i16) || TRI->hasType(*RC, MVT::v8f16)) Opc = Mips::ST_H; - else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32)) + else if (TRI->hasType(*RC, MVT::v4i32) || TRI->hasType(*RC, MVT::v4f32)) Opc = Mips::ST_W; - else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64)) + else if (TRI->hasType(*RC, MVT::v2i64) || TRI->hasType(*RC, MVT::v2f64)) Opc = Mips::ST_D; else if (Mips::LO32RegClass.hasSubClassEq(RC)) Opc = Mips::SW; @@ -280,13 +280,13 @@ loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Opc = Mips::LDC1; else if (Mips::FGR64RegClass.hasSubClassEq(RC)) Opc = Mips::LDC164; - else if (RC->hasType(MVT::v16i8)) + else if (TRI->hasType(*RC, MVT::v16i8)) Opc = Mips::LD_B; - else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16)) + else if (TRI->hasType(*RC, MVT::v8i16) || TRI->hasType(*RC, MVT::v8f16)) Opc = Mips::LD_H; - else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32)) + else if (TRI->hasType(*RC, MVT::v4i32) || TRI->hasType(*RC, MVT::v4f32)) Opc = Mips::LD_W; - else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64)) + else if (TRI->hasType(*RC, MVT::v2i64) || TRI->hasType(*RC, MVT::v2f64)) Opc = Mips::LD_D; else if (Mips::HI32RegClass.hasSubClassEq(RC)) Opc = Mips::LW; |
