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* [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-111-0/+17
| | | | | | The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection. llvm-svn: 190507
* [mips][msa] Separate the configuration of int/float vector types since they ↵Daniel Sanders2013-09-111-8/+22
| | | | | | | | will diverge soon No functional change llvm-svn: 190506
* [mips] When double precision loads and stores are split into two i32 loads andAkira Hatanaka2013-09-091-3/+3
| | | | | | | stores, make sure the load or store that accesses the higher half does not have an alignment that is larger than the offset from the original address. llvm-svn: 190318
* [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index doubleAkira Hatanaka2013-09-071-0/+74
| | | | | | | | | | precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. llvm-svn: 190235
* Fix a problem with dual mips16/mips32 mode. When the underlying processorReed Kotler2013-08-301-1/+1
| | | | | | | | | | | | | has hard float, when you compile the mips32 code you have to make sure that it knows to compile any mips32 routines as hard float. I need to clean up the way mips16 hard float is specified but I need to first think through all the details. Mips16 always has a form of soft float, the difference being whether the underlying hardware has floating point. So it's not really necessary to pass the -soft-float to llvm since soft-float is always true for mips16 by virtue of the fact that it will not register floating point registers. By using this fact, I can simplify the way this is all handled. llvm-svn: 189690
* [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.vDaniel Sanders2013-08-281-1/+113
| | | | | | | | | | | | | These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
* [mips][msa] Added load/store intrinsics.Daniel Sanders2013-08-281-1/+61
| | | | llvm-svn: 189476
* [mips][msa] Split MSA128 regset into size-specific sets containing the same ↵Daniel Sanders2013-08-231-10/+10
| | | | | | registers. llvm-svn: 189095
* [mips] Add support for calling convention CC_MipsO32_FP64, which is used ↵Akira Hatanaka2013-08-201-1/+1
| | | | | | | | | | when the size of floating point registers is 64-bit. Test case will be added when support for mfhc1 and mthc1 is added. llvm-svn: 188847
* [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)Jack Carter2013-08-151-14/+19
| | | | | | | | | | | | | Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
* [mips] Rename DSPRegs.Akira Hatanaka2013-08-141-1/+1
| | | | llvm-svn: 188342
* [Mips][msa] Added initial MSA support.Jack Carter2013-08-131-0/+17
| | | | | | | | | | | | * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-3/+3
| | | | llvm-svn: 187832
* [mips] Expand vector truncating stores and extending loads.Akira Hatanaka2013-08-021-0/+14
| | | | llvm-svn: 187667
* [mips] Improve code generation for constant multiplication using shifts, ↵Akira Hatanaka2013-06-261-0/+54
| | | | | | | | adds and subs. llvm-svn: 185011
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-9/+9
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* [mips] Instruction selection patterns for DSP-ASE vector select and compareAkira Hatanaka2013-04-301-2/+61
| | | | | | instructions. llvm-svn: 180820
* [mips] Compare splat value with element size instead of calling isUIntN.Akira Hatanaka2013-04-231-2/+2
| | | | | | No intended changes in functionality. llvm-svn: 180130
* 80 columns.Akira Hatanaka2013-04-221-3/+4
| | | | llvm-svn: 180040
* [mips] In performDSPShiftCombine, check that all elements in the vector areAkira Hatanaka2013-04-221-3/+5
| | | | | | | shifted by the same amount and the shift amount is smaller than the element size. llvm-svn: 180039
* Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover2013-04-201-1/+0
| | | | llvm-svn: 179939
* [mips] Instruction selection patterns for DSP-ASE vector shifts.Akira Hatanaka2013-04-191-0/+63
| | | | llvm-svn: 179906
* [mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN andAkira Hatanaka2013-04-131-0/+171
| | | | | | | | lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering. No functionality changes. llvm-svn: 179444
* [mips] Reapply r179420 and r179421.Akira Hatanaka2013-04-131-0/+5
| | | | llvm-svn: 179434
* Revert r179420 and r179421.Akira Hatanaka2013-04-121-5/+0
| | | | llvm-svn: 179422
* [mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.Akira Hatanaka2013-04-121-0/+5
| | | | llvm-svn: 179420
* [mips] Custom-lower i64 MULHS and MULHU nodes. Remove the code which selectsAkira Hatanaka2013-04-111-1/+4
| | | | | | | | multiply instructions in MipsSEDAGToDAGISel. This patch was supposed to be part of r178403. llvm-svn: 179314
* This patch enables llvm to switch between compiling for mips32/mips64 Reed Kotler2013-04-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and mips16 on a per function basis. Because this patch is somewhat involved I have provide an overview of the key pieces of it. The patch is written so as to not change the behavior of the non mixed mode. We have tested this a lot but it is something new to switch subtargets so we don't want any chance of regression in the mainline compiler until we have more confidence in this. Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1. For that reason there are derived versions of the register info, frame info, instruction info and instruction selection classes. Now we register three separate passes for instruction selection. One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and MipsSEISelDAGToDAG.cpp). When the ModuleISel pass runs, it determines if there is a need to switch subtargets and if so, the owning pointers in MipsTargetMachine are appropriately changed. When 16Isel or SEIsel is run, they will return immediately without doing any work if the current subtarget mode does not apply to them. In addition, MipsAsmPrinter needs to be reset on a function basis. The pass BasicTargetTransformInfo is substituted with a null pass since the pass is immutable and really needs to be a function pass for it to be used with changing subtargets. This will be fixed in a follow on patch. llvm-svn: 179118
* Remove unused variables.Akira Hatanaka2013-03-301-2/+0
| | | | llvm-svn: 178405
* [mips] Move the code which does dag-combine for multiply-add/sub nodes toAkira Hatanaka2013-03-301-0/+197
| | | | | | | | | derived class MipsSETargetLowering. We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16 doesn't have support for multipy-add/sub instructions. llvm-svn: 178404
* [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.Akira Hatanaka2013-03-301-0/+50
| | | | | | | | | The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. llvm-svn: 178403
* [mips] Fix filename in comment and delete unnecessary lines of code.Akira Hatanaka2013-03-141-5/+1
| | | | | | No functionality changes. llvm-svn: 177104
* [mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is forAkira Hatanaka2013-03-131-0/+201
mips16 and MipsSETargetLowering is for mips32/64. No functionality changes. llvm-svn: 176917
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