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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-20 23:38:40 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-20 23:38:40 +0000 |
| commit | bfb6624797b94b545b3124a5b3bd5b96e69abb92 (patch) | |
| tree | 0e86fe348da8b867e735ac2b26923708162a735b /llvm/lib/Target/Mips/MipsSEISelLowering.cpp | |
| parent | b83435260931860a30e4a09ebe0837522874909f (diff) | |
| download | bcm5719-llvm-bfb6624797b94b545b3124a5b3bd5b96e69abb92.tar.gz bcm5719-llvm-bfb6624797b94b545b3124a5b3bd5b96e69abb92.zip | |
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the
size of floating point registers is 64-bit.
Test case will be added when support for mfhc1 and mthc1 is added.
llvm-svn: 188847
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSEISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index 750ec0e0d33..fb722515c87 100644 --- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -92,7 +92,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) // When dealing with single precision only, use libcalls if (!Subtarget->isSingleFloat()) { - if (HasMips64) + if (Subtarget->isFP64bit()) addRegisterClass(MVT::f64, &Mips::FGR64RegClass); else addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); |
