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* GlobalISel: Remove unsigned variant of SrcOpMatt Arsenault2019-06-241-2/+2
| | | | | | | | | Force using Register. One downside is the generated register enums require explicit conversion. llvm-svn: 364194
* [MIPS GlobalISel] Handle position independent code Petar Avramovic2019-05-311-0/+1
| | | | | | | | | | | | | Handle position independent code for MIPS32. When callee is global address, lower call will emit callee as G_GLOBAL_VALUE and add target flag if needed. Support $gp in getRegBankFromRegClass(). Select G_GLOBAL_VALUE, specially handle case when there are target flags attached by lowerCall. Differential Revision: https://reviews.llvm.org/D62589 llvm-svn: 362210
* [mips] Move initGlobalBaseReg to MipsFunctionInfo. NFCPetar Avramovic2019-05-311-0/+4
| | | | | | | | | | | Move initGlobalBaseReg from MipsSEDAGToDAGISel to MipsFunctionInfo. This way functions used for handling position independent code during instruction selection, getGlobalBaseReg and initGlobalBaseReg, end up in same class. Differential Revision: https://reviews.llvm.org/D62586 llvm-svn: 362206
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [Mips] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-01-301-20/+14
| | | | | | other minor fixes (NFC). llvm-svn: 293565
* [mips][mips16] Fix machine verifier errors about incorrect register classes ↵Daniel Sanders2016-06-161-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on load/stores. Summary: [ls][bh] and [ls][bh]u cannot use sp-relative addresses and must therefore lower frameindex nodes such that there is a copy to a CPU16Regs register. This is now done consistently using a separate addressing mode that does not permit frameindex nodes. As part of this I've had to remove an optimization that reduced the number of instructions needed to work around the lack of sp-relative addresses on [ls][bh] and [ls][bh]u. This optimization used one of the eight CPU16Regs registers as a copy of the stack pointer and it's implementation was the root cause of many of the register vs register class mismatches. lw/sw can use sp-relative addresses but we ought to ensure that we use the correct version of lw/sw internally for things like IAS. This is not currently the case and this change does not fix this. However, this change does clean it up sufficiently well to fix the machine verifier failures. Also removed irrelevant functions from stchar.ll. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21062 llvm-svn: 272882
* [NFC] Header cleanupMehdi Amini2016-04-181-3/+0
| | | | | | | | | | | | | | Removed some unused headers, replaced some headers with forward class declarations. Found using simple scripts like this one: clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap' Patch by Eugene Kosov <claprix@yandex.ru> Differential Revision: http://reviews.llvm.org/D19219 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 266595
* [mips] Interrupt attribute support for mips32r2+.Vasileios Kalintiris2015-10-261-1/+15
| | | | | | | | | | | | | | | | | | | Summary: This patch adds support for using the "interrupt" attribute on Mips for interrupt handling functions. At this time only mips32r2+ with the o32 ABI with the static relocation model is supported. Unsupported configurations will be rejected Patch by Simon Dardis (+ clang-format & some trivial changes to follow the LLVM coding standards by me). Reviewers: mpf, dsanders Subscribers: dsanders, vkalintiris, llvm-commits Differential Revision: http://reviews.llvm.org/D10768 llvm-svn: 251286
* PseudoSourceValue: Transform the mips subclass to target independent subclassesAlex Lorenz2015-08-111-30/+5
| | | | | | | | | | | | This commit transforms the mips-specific 'MipsCallEntry' subclass of the 'PseudoSourceValue' class into two, target-independent subclasses named 'GlobalValuePseudoSourceValue' and 'ExternalSymbolPseudoSourceValue'. This change makes it easier to serialize the pseudo source values by removing target-specific pseudo source values. Reviewers: Akira Hatanaka llvm-svn: 244698
* [Mips] Use unique_ptr to manage ownership.Benjamin Kramer2015-04-161-2/+3
| | | | | | | Required some tweaking of ValueMap to accommodate a move-only value type. No functional change intended. llvm-svn: 235091
* Fix some cases where StringRef was being passed by const reference. Remove ↵Craig Topper2014-08-301-2/+2
| | | | | | const from some other StringRefs since its implicitly const already. llvm-svn: 216820
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* [mips] For the FP64A ABI, odd-numbered double-precision moves must not use ↵Daniel Sanders2014-07-141-3/+3
| | | | | | | | | | | | | | | | | | | | | mtc1/mfc1. Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers to the upper 32-bits of the corresponding even register. In effect, simulating FR=0 mode when FR=0 mode is not available. Unfortunately, we have to make the decision to avoid mfc1/mtc1 before register allocation so we currently do this for even registers too. FPXX has a similar requirement on 32-bit architectures that lack mfhc1/mthc1 so this patch also handles the affected moves from the FPU for FPXX too. Moves to the FPU were supported by an earlier commit. Differential Revision: http://reviews.llvm.org/D4484 llvm-svn: 212938
* [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI isSasa Stankovic2014-07-141-1/+8
| | | | | | | | | | | | | | | enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1) This prevents the upper 32-bits of a double precision value from being moved to the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure that the code generated executes correctly regardless of the current FPU mode. MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue to use dmtc1. Differential Revision: http://reviews.llvm.org/D4465 llvm-svn: 212930
* Remove unnecessary include.Eric Christopher2014-07-021-1/+0
| | | | llvm-svn: 212150
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-4/+4
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
* [Modules] Move ValueMap to the IR library. While this class does notChandler Carruth2014-03-041-1/+1
| | | | | | | | | | | | directly care about the Value class (it is templated so that the key can be any arbitrary Value subclass), it is in fact concretely tied to the Value class through the ValueHandle's CallbackVH interface which relies on the key type being some Value subclass to establish the value handle chain. Ironically, the unittest is already in the right library. llvm-svn: 202824
* This patch has two main functions:Reed Kotler2014-02-141-4/+15
| | | | | | | | | | | | | | | | | 1) Fix a specific bug when certain conversion functions are called in a program compiled as mips16 with hard float and the program is linked as c++. There are two libraries that are reversed in the link order with gcc/g++ and clang/clang++ for mips16 in this case and the proper stubs will then not be called. These stubs are normally handled in the Mips16HardFloat pass but in this case we don't know at that time that we need to generate the stubs. This must all be handled later in code generation and we have moved this functionality to MipsAsmPrinter. When linked as C (gcc or clang) the proper stubs are linked in from libc. 2) Set up the infrastructure to handle 90% of what is in the Mips16HardFloat pass in this new area of MipsAsmPrinter. This is a more logical place to handle this and we have known for some time that we needed to move the code later and not implement it using inline asm as we do now but it was not clear exactly where to do this and what mechanism should be used. Now it's clear to us how to do this and this patch contains the infrastructure to move most of this to MipsAsmPrinter but the actual moving will be done in a follow on patch. The same infrastructure is used to fix this current bug as described in #1. This change was requested by the list during the original putback of the Mips16HardFloat pass but was not practical for us do at that time. llvm-svn: 201426
* [mips] Define a derived class of PseudoSourceValue that represents a GOT entryAkira Hatanaka2013-09-271-0/+37
| | | | | | resolved by lazy-binding. llvm-svn: 191578
* [mips] Move public functions to the beginning of the class definition.Akira Hatanaka2013-09-251-33/+33
| | | | | | No intended functionality change. llvm-svn: 191352
* [mips] Lower EH_RETURN.Akira Hatanaka2013-01-301-1/+15
| | | | | | Patch by Sasa Stankovic. llvm-svn: 173862
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-041-1/+1
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Delete MipsFunctionInfo::NextStackOffset. No functionality change intended. Akira Hatanaka2012-11-071-7/+4
| | | | llvm-svn: 167546
* [mips] Add member field MipsFunctionInfo::IncomingArgSize which holds the sizeAkira Hatanaka2012-11-021-0/+6
| | | | | | of the incoming argument area. llvm-svn: 167312
* [mips] Delete MipsFunctionInfo::EmitNOAT. Unconditionally print directiveAkira Hatanaka2012-11-021-6/+1
| | | | | | | "set .noat" so that the assembler doesn't issue warnings when register $AT is used. llvm-svn: 167310
* Add code for saving formal argument information to MipsFunctionInfo. ThisAkira Hatanaka2012-10-301-0/+11
| | | | | | | information will be used by IsEligibleForTailCallOptimization to determine whether a call can be tail-call optimized. llvm-svn: 167043
* This patch is for the implementation of mips16 complex pattern addr16.Reed Kotler2012-10-281-2/+10
| | | | | | | | | | | | | | | | | | | | | Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. llvm-svn: 166897
* Delete MipsFunctionInfo::InArgFIRange. Akira Hatanaka2012-10-261-11/+1
| | | | llvm-svn: 166837
* [mips] Delete MipsFunctionInfo::MaxCallFrameSize which is no longer used.Akira Hatanaka2012-10-191-6/+1
| | | | llvm-svn: 166339
* Delete member MipsFunctionInfo::OutArgFIRange and code that accesses it.Akira Hatanaka2012-09-261-14/+2
| | | | llvm-svn: 164718
* Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.Akira Hatanaka2012-07-311-13/+1
| | | | | | | The frame object which points to the dynamically allocated area will not be needed after changes are made to cease reserving call frames. llvm-svn: 161076
* Eliminate the stack slot used to save the global base register.Akira Hatanaka2012-07-251-20/+1
| | | | | | | | The long branch pass (fixed in r160601) no longer uses the global base register to compute addresses of branch destinations, so it is not necessary to reserve a slot on the stack. llvm-svn: 160703
* Add methods to MipsFunctionInfo for initializing and accessing the stack frameAkira Hatanaka2012-06-141-1/+23
| | | | | | | | | object for the global base register. This is the first of a series of patches which implements long branch expansion for MIPS. llvm-svn: 158427
* Delete all functions that are no longer needed in MipsFunctionInfo, includingAkira Hatanaka2012-05-121-8/+1
| | | | | | | | | the ones that get or set the frame index for the $gp save slot. Remove the piece of code in MipsFunctionInfo::getGlobalBaseReg() which returns GP. This function should always return a virtual register. llvm-svn: 156695
* Add member EmitNOAT and its setter and getter functions to class ↵Akira Hatanaka2012-03-271-1/+6
| | | | | | | | | MipsFunctionInfo. If EmitNOAT is true, directives ".set noat" and ".set at" are emitted at the beginning and end of a function. llvm-svn: 153528
* Prune some includesCraig Topper2012-03-271-1/+0
| | | | llvm-svn: 153502
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-1/+1
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* remove blanks, and some code formatJia Liu2012-02-281-4/+4
| | | | llvm-svn: 151625
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-241-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* Remove VectorExtras. This unused helper was written for a type of API that ↵Benjamin Kramer2012-01-071-1/+0
| | | | | | is discouraged now. llvm-svn: 147738
* Unweaken vtables as per ↵David Blaikie2011-12-201-1/+1
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Remove variable that keeps the size of area used to save byval or variableAkira Hatanaka2011-11-141-10/+1
| | | | | | | | | | | argument registers on the callee's stack frame, along with functions that set and get it. It is not necessary to add the size of this area when computing stack size in emitPrologue, since it has already been accounted for in PEI::calculateFrameObjectOffsets. llvm-svn: 144549
* Define functions that get or set the size of area on callee's stack frame whichAkira Hatanaka2011-11-071-1/+10
| | | | | | is used to save va_arg or byval arguments passed in registers. llvm-svn: 143992
* Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from Akira Hatanaka2011-07-181-8/+1
| | | | | | | | moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. llvm-svn: 135415
* Re-apply 132758 and 132768 which were speculatively reverted in 132777. Akira Hatanaka2011-06-211-3/+15
| | | | llvm-svn: 133494
* Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.Eric Christopher2011-06-091-15/+3
| | | | llvm-svn: 132777
* Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of theAkira Hatanaka2011-06-081-3/+15
| | | | | | dynamically allocated stack area was not set. llvm-svn: 132758
* This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,Bruno Cardoso Lopes2011-05-311-1/+10
| | | | | | | | | | nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
* Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check ifAkira Hatanaka2011-05-261-6/+1
| | | | | | a function has any function calls. llvm-svn: 132140
* Change initial value of MaxCallFrameSize. MipsFI::getMaxCallFrameSize() shouldAkira Hatanaka2011-05-251-4/+4
| | | | | | return 0 if there are no function calls made. llvm-svn: 132065
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