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* Fix PR5149.Bruno Cardoso Lopes2009-11-091-0/+1
| | | | | | http://llvm.org/bugs/show_bug.cgi?id=5149 llvm-svn: 86543
* Major calling convention code refactoring.Dan Gohman2009-08-051-2/+2
| | | | | | | | | | | | | | | | | | | Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
* Convert Alpha and Mips to use a MachineFunctionInfo subclass toDan Gohman2009-06-031-1/+9
| | | | | | | | | | carry GlobalBaseReg, and GlobalRetAddr too in Alpha's case. This eliminates the need for them to search through the MachineRegisterInfo livein list in order to identify these virtual registers. EmitLiveInCopies is now the only user of the virtual register portion of MachineRegisterInfo's livein data. llvm-svn: 72802
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-051-0/+1
| | | | llvm-svn: 61715
* Added support for fp callee saved registers.Bruno Cardoso Lopes2008-08-061-11/+20
| | | | | | | | | | | | | | | | | | | | | Added fp register clobbering during calls. Added AsmPrinter support for "fmask", a bitmask that indicates where on the stack the fp callee saved registers are. Fixed the stack frame layout for Mips, now the callee saved regs are in the right stack location (a little documentation about how this stack frame must look like is present in MipsRegisterInfo.cpp). This was done using the method MipsRegisterInfo::adjustMipsStackFrame To be more clear, these are examples of what is solves : 1) FP and RA are also callee saved, and despite they aren't in CSI they must be saved before the fp callee saved registers. 2) The ABI requires that local varibles are allocated before the callee saved register area, the opposite behavior from the default allocation. 3) CPU and FPU saved register area must be aligned independent of each other. llvm-svn: 54403
* Several changes to Mips backend, experimental fp support being the mostBruno Cardoso Lopes2008-07-051-18/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Added support for PIC code with "explicit relocations" *only*.Bruno Cardoso Lopes2007-11-051-8/+12
| | | | | | | Removed all macro code for PIC (goodbye "la"). Support tested with shootout bench. llvm-svn: 43697
* Position Independent Code (PIC) support [2]Bruno Cardoso Lopes2007-10-091-0/+8
| | | | | | | | | | - Added a function to hold the stack location where GP must be stored during LowerCALL - AsmPrinter now emits directives based on relocation type - PIC_ set to default relocation type (same as GCC) llvm-svn: 42779
* Added methods to record SPOffsets from LowerFORMAL_ARGUMENTSBruno Cardoso Lopes2007-08-281-3/+53
| | | | llvm-svn: 41525
* Added MipsMachineFunction class, to hold Mips dinamic stack info when ↵Bruno Cardoso Lopes2007-07-111-0/+54
inserting Prologue/Epilog llvm-svn: 39758
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