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path: root/llvm/lib/Target/Mips/MipsMCInstLower.cpp
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* There are some Mips instructions that are lowered by the Jack Carter2012-09-061-68/+0
| | | | | | | | | | | | | | | | assembler such as shifts greater than 32. In the case of direct object, the code gen needs to do this lowering since the assembler is not involved. With the advent of the llvm-mc assembler, it also needs to do the same lowering. This patch makes that specific lowering code accessible to both the direct object output and the assembler. This patch does not affect generated output. llvm-svn: 163287
* The instruction DINS may be transformed into DINSU or DEXTM dependingJack Carter2012-08-311-19/+23
| | | | | | | | | | | | | | | | | | | | | on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword llvm-svn: 163010
* The instruction DEXT may be transformed into DEXTU or DEXTM dependingJack Carter2012-08-281-0/+35
| | | | | | | | | | | | | | | | | | | | | on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword llvm-svn: 162782
* Add HIGHER and HIGHEST relocations to Mips backend.Akira Hatanaka2012-07-211-0/+2
| | | | llvm-svn: 160599
* Doubleword Shift Left Logical Plus 32Jack Carter2012-07-161-0/+29
| | | | | | | | | | | | | | | | | | | | | Mips shift instructions DSLL, DSRL and DSRA are transformed into DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between 32 and 63 Here is a description of DSLL: Purpose: Doubleword Shift Left Logical Plus 32 To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits Description: GPR[rd] <- GPR[rt] << (sa+32) The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the emptied bits; the result is placed in GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa. This patch implements the direct object output of these instructions. llvm-svn: 160277
* Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka2012-06-141-7/+7
| | | | llvm-svn: 158471
* Remove code in MipsAsmPrinter and MipsMCInstLower.Akira Hatanaka2012-06-141-20/+2
| | | | llvm-svn: 158434
* Remove code which is no longer needed in MipsAsmPrinter and MipsMCInstLower.Akira Hatanaka2012-06-021-112/+0
| | | | llvm-svn: 157867
* In MipsMCInstLower::LowerSymbolOperand, get offset from symbol ifAkira Hatanaka2012-06-021-2/+4
| | | | | | the MachineOperand type has a valid offset. llvm-svn: 157861
* Remove the code that expands MIPS' .cpload directive.Akira Hatanaka2012-05-251-23/+0
| | | | llvm-svn: 157494
* Remove the code that emits MIPS' .cprestore directive.Akira Hatanaka2012-05-251-27/+0
| | | | llvm-svn: 157493
* Make the following changes in MipsAsmPrinter.cpp:Akira Hatanaka2012-05-121-10/+5
| | | | | | | | | - Remove code which lowers pseudo SETGP01. - Fix LowerSETGP01. The first two of the three instructions that are emitted to initialize the global pointer register now use register $2. - Stop emitting .cpload directive. llvm-svn: 156689
* Emit all directives except for ".cprestore" during asm printing rather than emitAkira Hatanaka2012-03-281-63/+57
| | | | | | | | | | | | | | | | them as machine instructions. Directives ".set noat" and ".set at" are now emitted only at the beginning and end of a function except in the case where they are emitted to enclose .cpload with an immediate operand that doesn't fit in 16-bit field or unaligned load/stores. Also, make the following changes: - Remove function isUnalignedLoadStore and use a switch-case statement to determine whether an instruction is an unaligned load or store. - Define helper function CreateMCInst which generates an instance of an MCInst from an opcode and a list of operands. llvm-svn: 153552
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-1/+1
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* remove blanks, and some code formatJia Liu2012-02-281-9/+9
| | | | llvm-svn: 151625
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-241-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-171-1/+1
| | | | llvm-svn: 150805
* add Emacs tag and fix some comment error in file headersJia Liu2012-02-171-1/+1
| | | | llvm-svn: 150775
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-5/+3
| | | | llvm-svn: 149961
* Ignore register mask operands when lowering instructions to MC.Jakob Stoklund Olesen2012-01-181-0/+2
| | | | | | | This is similar to implicit register operands. MC doesn't understand register liveness and call clobbers. llvm-svn: 148437
* Cleanup Mips code and rename some variables. Patch by Jack CarterBruno Cardoso Lopes2011-12-301-73/+73
| | | | llvm-svn: 147383
* Tidy up. Simplify logic. No functional change intended.Akira Hatanaka2011-12-191-20/+20
| | | | llvm-svn: 146896
* Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct objectAkira Hatanaka2011-12-141-0/+3
| | | | | | | emission is not supported yet, but a patch that adds the support should follow soon. llvm-svn: 146572
* Expand .cprestore directive to multiple instructions if the offset does not fit Akira Hatanaka2011-12-131-6/+27
| | | | | | in a 16-bit field. llvm-svn: 146469
* Add a few moreLocal/Global R_MIPS_GOT related fixups andBruno Cardoso Lopes2011-12-071-0/+1
| | | | | | | | make the addend fixup code a bit more generic Patch by Jack Carter. llvm-svn: 145998
* This patch makes the following changes necessary for MIPS' direct code emission.Akira Hatanaka2011-11-231-32/+146
| | | | | | | | - lower unaligned loads/stores. - encode the size operand of instructions INS and EXT. - emit relocation information needed for JAL (jump-and-link). llvm-svn: 145113
* Mips MC object code emission improvements:Bruno Cardoso Lopes2011-11-111-0/+1
| | | | | | | | | | "With this patch we can now generate runnable Mips code through LLVM direct object emission. We have run numerous simple programs, both C and C++ and with -O0 and -O3 from the output. The code is not production ready, but quite useful for experimentation." Patch and message by Jack Carter llvm-svn: 144414
* Properly handle Mips MC relocations and lower cpload and cprestore macros to ↵Bruno Cardoso Lopes2011-11-081-20/+77
| | | | | | | | MCInsts. Patch by Jack Carter. llvm-svn: 144139
* Add enums and functions for symbols Mips64 uses.Akira Hatanaka2011-09-221-0/+5
| | | | llvm-svn: 140295
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-091-44/+0
| | | | llvm-svn: 139405
* Fix handling of double precision loads and stores when Mips1 is targeted. Akira Hatanaka2011-08-161-0/+44
| | | | | | | | | | | | | | | Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. llvm-svn: 137711
* Define function MipsMCInstLower::LowerOperand. Akira Hatanaka2011-08-161-25/+28
| | | | llvm-svn: 137707
* Add parameter Offset to MipsMCInstLower::LowerSymbolOperand. Akira Hatanaka2011-08-161-4/+4
| | | | llvm-svn: 137706
* Raise assertion when MachineOperand has unexpected target flag.Akira Hatanaka2011-07-081-1/+2
| | | | llvm-svn: 134671
* Make sure variable Kind is assigned a value to suppress warning.Akira Hatanaka2011-07-081-1/+1
| | | | llvm-svn: 134668
* Define class MipsMCInstLower.Akira Hatanaka2011-07-071-0/+117
llvm-svn: 134633
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