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authorAkira Hatanaka <ahatanaka@mips.com>2012-05-12 00:48:43 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2012-05-12 00:48:43 +0000
commit8f3573034b4950d26b4222fa909c288e7f2c38c0 (patch)
tree2f128a7e92aa429d39b23f79b572d19bb80ad938 /llvm/lib/Target/Mips/MipsMCInstLower.cpp
parent10702d5f2225ec8da11cd1ef687f0bf958b53ba0 (diff)
downloadbcm5719-llvm-8f3573034b4950d26b4222fa909c288e7f2c38c0.tar.gz
bcm5719-llvm-8f3573034b4950d26b4222fa909c288e7f2c38c0.zip
Make the following changes in MipsAsmPrinter.cpp:
- Remove code which lowers pseudo SETGP01. - Fix LowerSETGP01. The first two of the three instructions that are emitted to initialize the global pointer register now use register $2. - Stop emitting .cpload directive. llvm-svn: 156689
Diffstat (limited to 'llvm/lib/Target/Mips/MipsMCInstLower.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsMCInstLower.cpp15
1 files changed, 5 insertions, 10 deletions
diff --git a/llvm/lib/Target/Mips/MipsMCInstLower.cpp b/llvm/lib/Target/Mips/MipsMCInstLower.cpp
index 1597b933445..8bdcfd9bc25 100644
--- a/llvm/lib/Target/Mips/MipsMCInstLower.cpp
+++ b/llvm/lib/Target/Mips/MipsMCInstLower.cpp
@@ -317,16 +317,11 @@ void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
if (!TwoInstructions) MCInsts.push_back(Instr3);
}
-// Convert
-// "setgp01 $reg"
-// to
-// "lui $reg, %hi(_gp_disp)"
-// "addiu $reg, $reg, %lo(_gp_disp)"
-void MipsMCInstLower::LowerSETGP01(const MachineInstr *MI,
- SmallVector<MCInst, 4>& MCInsts) {
- const MachineOperand &MO = MI->getOperand(0);
- assert(MO.isReg());
- MCOperand RegOpnd = MCOperand::CreateReg(MO.getReg());
+// Create the following two instructions:
+// "lui $2, %hi(_gp_disp)"
+// "addiu $2, $2, %lo(_gp_disp)"
+void MipsMCInstLower::LowerSETGP01(SmallVector<MCInst, 4>& MCInsts) {
+ MCOperand RegOpnd = MCOperand::CreateReg(Mips::V0);
StringRef SymName("_gp_disp");
const MCSymbol *Sym = Ctx->GetOrCreateSymbol(SymName);
const MCSymbolRefExpr *MCSym;
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