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* [mips] Merge MipsLongBranch and MipsHazardSchedule passesAleksandar Beserminji2018-05-221-632/+0
| | | | | | | | | | | | | | MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it potentially breaks some jumps, so they have to be expanded to long branches. When some branch is expanded to long branch, it potentially creates a hazard situation, which should be fixed by adding nops. New pass is called MipsBranchExpansion, it combines these two passes, and runs them alternately until one of them reports no changes were made. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332977
* [mips] Revert Merge MipsLongBranch and MipsHazardSchedule passesAleksandar Beserminji2018-05-211-0/+632
| | | | | | | | Revert this patch due buildbot failure. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332837
* [mips] Merge MipsLongBranch and MipsHazardSchedule passesAleksandar Beserminji2018-05-211-632/+0
| | | | | | | | | | | | | | MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it potentially breaks some jumps, so they have to be expanded to long branches. When some branch is expanded to long branch, it potentially creates a hazard situation, which should be fixed by adding nops. New pass is called MipsBranchExpansion, it combines these two passes, and runs them alternately until one of them reports no changes were made. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332834
* [mips] Add support for isBranchOffsetInRange and use it for MipsLongBranchSimon Dardis2018-05-161-4/+4
| | | | | | | | | | | | Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along with some tests. Also add missing getOppositeBranchOpc() cases exposed by the tests. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46794 llvm-svn: 332446
* [mips] Initialize the long branch pass for testing purposesSimon Dardis2018-05-121-2/+6
| | | | llvm-svn: 332172
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-1/+1
| | | | | | | | | | | | | | | | | | Because we create a new kind of debug instruction, DBG_LABEL, we need to check all passes which use isDebugValue() to check MachineInstr is debug instruction or not. When expelling debug instructions, we should expel both DBG_VALUE and DBG_LABEL. So, I create a new function, isDebugInstr(), in MachineInstr to check whether the MachineInstr is debug instruction or not. This patch has no new test case. I have run regression test and there is no difference in regression test. Differential Revision: https://reviews.llvm.org/D45342 Patch by Hsiangkai Wang. llvm-svn: 331844
* Reland r331175: "[mips] Fix the predicates of jump and branch and link ↵Simon Dardis2018-05-011-1/+1
| | | | | | | | | | | | | | | | instructions" The previous version of this patch restricted the 'jal' instruction to MIPS and microMIPSr3. microMIPS32r6 does not have this instruction and instead uses jal as an alias for balc. Original commit message: > Reviewers: smaksimovic, atanasyan, abeserminji > > Differential Revision: https://reviews.llvm.org/D46114 > llvm-svn: 331259
* Revert "[mips] Fix the predicates of jump and branch and link instructions"Simon Dardis2018-04-301-1/+1
| | | | | | | | That commit broke one of the LLD builders, reverting while I investigate. This patch reverts r331175. llvm-svn: 331178
* [mips] Fix the predicates of jump and branch and link instructionsSimon Dardis2018-04-301-1/+1
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46114 llvm-svn: 331175
* [mips] Spectre variant two mitigation for MIPSR2Simon Dardis2018-02-211-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It implements the LLVM part of -mindirect-jump=hazard. It is _not_ enabled by default for the P5600. The migitation strategy suggested by MIPS for these processors is to use hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the attribute +use-indirect-jump-hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Performance benchmarking of this option with -fpic and lld using -z hazardplt shows a difference of overall 10%~ time increase for the LLVM testsuite. Certain benchmarks such as methcall show a substantially larger increase in time due to their nature. Reviewers: atanasyan, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D43486 llvm-svn: 325653
* [mips] Add partial support for R6 in the long branch passSimon Dardis2017-12-141-46/+116
| | | | | | | | | | | | | | | | | | | | MIPSR6 introduced several new jump instructions and deprecated the use of the 'j' instruction. For microMIPS32R6, 'j' was removed entirely and it only has non delay slot jumps. This patch adds support for MIPSR6 by using some R6 instructions-- 'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'-- and modifies the sequences not to use delay slots for R6. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: dschuff, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D40786 llvm-svn: 320703
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* [Mips] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-031-6/+7
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309993
* Revert r305382, it caused PR33513.Nico Weber2017-06-191-6/+6
| | | | llvm-svn: 305735
* [mips] Fix machine verifier errors in the long branch passSimon Dardis2017-06-141-6/+6
| | | | | | | | | | | | | | | This patch fixes two systemic machine verifier errors in the long branch pass. The first is the incorrect basic block successors and the second was the incorrect construction of several jump instructions. This partially resolves PR27458 and the associated PR32146. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D33378 llvm-svn: 305382
* [LegacyPassManager] Remove TargetMachine constructorsFrancis Visoiu Mistrih2017-05-181-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides a new way to access the TargetMachine through TargetPassConfig, as a dependency. The patterns replaced here are: * Passes handling a null TargetMachine call `getAnalysisIfAvailable<TargetPassConfig>`. * Passes not handling a null TargetMachine `addRequired<TargetPassConfig>` and call `getAnalysis<TargetPassConfig>`. * MachineFunctionPasses now use MF.getTarget(). * Remove all the TargetMachine constructors. * Remove INITIALIZE_TM_PASS. This fixes a crash when running `llc -start-before prologepilog`. PEI needs StackProtector, which gets constructed without a TargetMachine by the pass manager. The StackProtector pass doesn't handle the case where there is no TargetMachine, so it segfaults. Related to PR30324. Differential Revision: https://reviews.llvm.org/D33222 llvm-svn: 303360
* [Mips] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-02-011-15/+29
| | | | | | other minor fixes (NFC). llvm-svn: 293729
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-3/+1
| | | | llvm-svn: 283004
* CodeGen: Give MachineBasicBlock::reverse_iterator a handle to the current MIDuncan P. N. Exon Smith2016-09-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that MachineBasicBlock::reverse_instr_iterator knows when it's at the end (since r281168 and r281170), implement MachineBasicBlock::reverse_iterator directly on top of an ilist::reverse_iterator by adding an IsReverse template parameter to MachineInstrBundleIterator. This replaces another hard-to-reason-about use of std::reverse_iterator on list iterators, matching the changes for ilist::reverse_iterator from r280032 (see the "out of scope" section at the end of that commit message). MachineBasicBlock::reverse_iterator now has a handle to the current node and has obvious invalidation semantics. r280032 has a more detailed explanation of how list-style reverse iterators (invalidated when the pointed-at node is deleted) are different from vector-style reverse iterators like std::reverse_iterator (invalidated on every operation). A great motivating example is this commit's changes to lib/CodeGen/DeadMachineInstructionElim.cpp. Note: If your out-of-tree backend deletes instructions while iterating on a MachineBasicBlock::reverse_iterator or converts between MachineBasicBlock::iterator and MachineBasicBlock::reverse_iterator, you'll need to update your code in similar ways to r280032. The following table might help: [Old] ==> [New] delete &*RI, RE = end() delete &*RI++ RI->erase(), RE = end() RI++->erase() reverse_iterator(I) std::prev(I).getReverse() reverse_iterator(I) ++I.getReverse() --reverse_iterator(I) I.getReverse() reverse_iterator(std::next(I)) I.getReverse() RI.base() std::prev(RI).getReverse() RI.base() ++RI.getReverse() --RI.base() RI.getReverse() std::next(RI).base() RI.getReverse() (For more details, have a look at r280032.) llvm-svn: 281172
* MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun2016-08-251-1/+1
| | | | | | | | | | | | | compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
* TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFCSjoerd Meijer2016-07-281-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D22925 llvm-svn: 276997
* Reapply "Mips: Avoid implicit iterator conversions, NFC"Duncan P. N. Exon Smith2016-07-151-3/+3
| | | | | | | | | | This reverts commit r275562, effectively reapplying r275141. Doug Gilmore reported that there was an error when bisecting the Mips buildbot failure, and that r275141 was not to blame after all. Here is the green build: https://dmz-portal.mips.com/bb/builders/LLVM%20with%20integrated%20assembler%20and%20fPIC%20and%20-O0/builds/803 llvm-svn: 275643
* Revert r275141 - Mips: Avoid implicit iterator conversions, NFCDaniel Sanders2016-07-151-3/+3
| | | | | | It appears to have caused some failures in our buildbots. llvm-svn: 275562
* Mips: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-121-3/+3
| | | | | | | | | Avoid implicit conversions from MachineInstrBundleIterator to MachineInstr* in the Mips backend, mainly by preferring MachineInstr& over MachineInstr* when a pointer isn't nullable and using range-based for loops. llvm-svn: 275141
* Convert more cases to isPositionIndependent(). NFC.Rafael Espindola2016-06-281-8/+4
| | | | llvm-svn: 274021
* [mips] Emit a JALR with $rd equal to $zero, instead of a JR in MIPS32R6.Vasileios Kalintiris2016-06-181-15/+23
| | | | | | | | | | | | | | Summary: JR is an alias of JALR with $rd=0 in the R6 ISA. Also, this fixes recursive builds in MIPS32R6. Reviewers: dsanders, sdardis Subscribers: jfb, dschuff, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21370 llvm-svn: 273085
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-3/+4
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* [mips] More range-based for loops. NFC.Vasileios Kalintiris2016-04-151-2/+2
| | | | | | | There are still a couple more inside the MIPS target. I opted for a single commit in order to avoid spamming the list. llvm-svn: 266472
* Add MachineFunctionProperty checks for AllVRegsAllocated for target passesDerek Schuff2016-04-041-0/+5
| | | | | | | | | | | | | | Summary: This adds the same checks that were added in r264593 to all target-specific passes that run after register allocation. Reviewers: qcolombet Subscribers: jyknight, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18525 llvm-svn: 265313
* Normalize MBB's successors' probabilities in several locations.Cong Hou2015-12-131-1/+1
| | | | | | | | | | | | This patch adds some missing calls to MBB::normalizeSuccProbs() in several locations where it should be called. Those places are found by checking if the sum of successors' probabilities is approximate one in MachineBlockPlacement pass with some instrumented code (not in this patch). Differential revision: http://reviews.llvm.org/D15259 llvm-svn: 255455
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-011-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. (This is the second attempt to submit this patch. The first caused two assertion failures and was reverted. See https://llvm.org/bugs/show_bug.cgi?id=25687) The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254377
* Revert r254348: "Replace all weight-based interfaces in MBB with ↵Hans Wennborg2015-12-011-1/+2
| | | | | | | | | | probability-based interfaces, and update all uses of old interfaces." and the follow-up r254356: "Fix a bug in MachineBlockPlacement that may cause assertion failure during BranchProbability construction." Asserts were firing in Chromium builds. See PR25687. llvm-svn: 254366
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-011-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254348
* Mips: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-2/+2
| | | | llvm-svn: 250769
* Remove most of the TargetMachine::getSubtarget/getSubtargetImplEric Christopher2015-01-291-21/+16
| | | | | | | | | calls that don't take a Function argument from Mips. Notable exceptions: the AsmPrinter and MipsTargetObjectFile. The latter needs to be fixed, and the former will be fixed when the general AsmPrinter changes happen. llvm-svn: 227512
* Move the Mips target to storing the ABI in the TargetMachine ratherEric Christopher2015-01-261-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. llvm-svn: 227102
* [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructionsJozef Kolek2015-01-121-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D5271 llvm-svn: 225627
* Replace several 'assert(false' with 'llvm_unreachable' or fold a condition ↵Craig Topper2015-01-051-2/+1
| | | | | | into the assert. llvm-svn: 225160
* [mips][microMIPS] This patch implements functionality in MIPS delay slotJozef Kolek2014-11-211-5/+7
| | | | | | | | | | | filler such as if delay slot filler have to put NOP instruction into the delay slot of microMIPS BEQ or BNE instruction which uses the register $0, then instead of emitting NOP this instruction is replaced by the corresponding microMIPS compact branch instruction, i.e. BEQZC or BNEZC. Differential Revision: http://reviews.llvm.org/D3566 llvm-svn: 222580
* [mips] Replace MipsABIEnum with a MipsABIInfo class.Daniel Sanders2014-10-241-4/+4
| | | | | | | | | | | | | | | | | | | | | Summary: No functional change yet, it's just an object replacement for an enum. It will allow us to gather ABI information in a single place so that we can start testing for properties of the ABI's instead of the ABI itself. For example we will eventually be able to use: ABI.MinStackAlignmentInBytes() instead of: (isABI_N32() || isABI_N64()) ? 16 : 8 which is clearer and more maintainable. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3341 llvm-svn: 220568
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-021-0/+1
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-071-1/+0
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Nuke the old JIT.Rafael Espindola2014-08-071-0/+1
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-4/+4
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Make non-module passes unconditionally added in the passEric Christopher2014-07-181-1/+2
| | | | | | | manager for mips, and early exit if we don't want to do anything because of the current subtarget. llvm-svn: 213407
* [mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal ↵Daniel Sanders2014-06-131-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | is a normal instruction Summary: b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias for 'bgezal $zero, $offset') still remains with the same encoding it had prior to MIPS32r6/MIPS64r6. Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo. No changes were required to the CodeGen test that looks for BAL (test/CodeGen/Mips/longbranch.ll) since the new instruction has the same syntax. Depends on D4113 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4114 llvm-svn: 210898
* [mips] Modify long branch for NaCl:Sasa Stankovic2014-06-051-6/+30
| | | | | | | | | * Move the instruction that changes sp outside of the branch delay slot. * Bundle-align the target of indirect branch. Differential Revision: http://llvm-reviews.chandlerc.com/D3928 llvm-svn: 210262
* [mips] Optimize long branch for MIPS64 by removing %higher and %highest.Sasa Stankovic2014-05-271-18/+18
| | | | | | | | | | %higher and %highest can have non-zero values only for offsets greater than 2GB, which is highly unlikely, if not impossible when compiling a single function. This makes long branch for MIPS64 3 instructions smaller. Differential Revision: http://llvm-reviews.chandlerc.com/D3281.diff llvm-svn: 209678
* [mips] Fix MipsLongBranch pass to work when the offset from the branch to theSasa Stankovic2014-04-301-32/+44
| | | | | | | | | | | | | | target cannot be determined accurately. This is the case for NaCl where the sandboxing instructions are added in MC layer, after the MipsLongBranch pass. It is also the case when the code has inline assembly. Instead of calculating offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions that are resolved during the fixup. This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll and implements microMIPS CHECKs in a much simpler way in a file test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64. llvm-svn: 207656
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-2/+2
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
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