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path: root/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
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* Do not reserve $gp as a dedicated global base register if the target ABI is ↵Akira Hatanaka2012-02-281-1/+2
| | | | | | not O32. llvm-svn: 151614
* Add support for floating point base register + offset register addressing modeAkira Hatanaka2012-02-281-2/+9
| | | | | | load and store instructions. llvm-svn: 151611
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-241-4/+86
| | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... llvm-svn: 151402
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-171-1/+1
| | | | llvm-svn: 150805
* add Emacs tag and fix some comment error in file headersJia Liu2012-02-171-1/+1
| | | | llvm-svn: 150775
* Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. Akira Hatanaka2012-01-251-0/+42
| | | | | | | Add a test case to show fewer instructions are needed to load an immediate with the new way of loading immediates. llvm-svn: 148908
* Fix uninitialized variable warning.Chad Rosier2012-01-061-1/+1
| | | | llvm-svn: 147676
* Add function MipsDAGToDAGISel::SelectMULT and factor out code that generatesAkira Hatanaka2011-12-201-37/+47
| | | | | | | nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU nodes. llvm-svn: 147008
* Fix indentation.Akira Hatanaka2011-12-201-115/+115
| | | | llvm-svn: 147007
* Add code in MipsDAGToDAGISel for selecting constant +0.0.Akira Hatanaka2011-12-201-0/+6
| | | | | | MIPS64 can generate constant +0.0 with a single DMTC1 instruction. llvm-svn: 146999
* Revert part of r146995 that was accidentally commmitted.Akira Hatanaka2011-12-201-6/+0
| | | | llvm-svn: 146996
* 32-to-64-bit sign extension pattern.Akira Hatanaka2011-12-201-0/+6
| | | | llvm-svn: 146995
* Tidy up. Simplify logic. No functional change intended.Akira Hatanaka2011-12-191-4/+6
| | | | llvm-svn: 146896
* Remove the restriction on the first operand of the add node in SelectAddr.Akira Hatanaka2011-12-191-3/+1
| | | | | | | | | | | | | | | | | | This change reduces the number of instructions generated. For example, (load (add (sub $n0, $n1), (MipsLo got(s)))) results in the following sequence of instructions: 1. sub $n2, $n0, $n1 2. lw got(s)($n2) Previously, three instructions were needed. 1. sub $n2, $n0, $n1 2. addiu $n3, $n2, got(s) 3. lw 0($n3) llvm-svn: 146888
* Rename WrapperPIC. It is now used for both pic and static.Akira Hatanaka2011-12-091-1/+1
| | | | llvm-svn: 146232
* Implement 64-bit support for thread local storage handling.Akira Hatanaka2011-12-081-17/+23
| | | | | | | | | | - Modify lowering of global TLS address nodes. - Modify isel of ThreadPointer. - Wrap target global TLS address nodes that are operands of loads with WrapperPIC. - Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be substituted with other existing nodes. llvm-svn: 146175
* Fix comment.Akira Hatanaka2011-12-071-2/+1
| | | | llvm-svn: 146063
* Fix comment.Akira Hatanaka2011-12-071-1/+1
| | | | llvm-svn: 146062
* Fix 64-bit immediate patterns.Akira Hatanaka2011-12-071-2/+2
| | | | llvm-svn: 146059
* Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too.Akira Hatanaka2011-10-111-7/+10
| | | | llvm-svn: 141615
* Add support for 64-bit integer multiply instructions.Akira Hatanaka2011-10-031-4/+14
| | | | llvm-svn: 141017
* Change the names of functions isMips* to hasMips*.Akira Hatanaka2011-09-201-1/+1
| | | | llvm-svn: 140214
* Fix handling of double precision loads and stores when Mips1 is targeted. Akira Hatanaka2011-08-161-139/+0
| | | | | | | | | | | | | | | Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. llvm-svn: 137711
* When constant double 0.0 is lowered, make sure 0 is copied directly from an Akira Hatanaka2011-08-121-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | integer register to a floating point register. It is not valid to interpret the value of a floating pointer register as part of a double precision floating point value after a single precision floating point computational or move instruction stores its result to the register. - In the test case, the following code is generated before this patch is applied: mtc1 $zero, $f2 ; unformatted copy to $f2 mov.s $f0, $f2 ; $f0 is in single format sdc1 $f12, 0($sp) mov.s $f1, $f2 ; $f1 is in single format c.eq.d $f12, $f0 ; $f0 cannot be interpreted as double - The following code is generated after this patch is applied: mtc1 $zero, $f0 ; unformatted copy to $f0 mtc1 $zero, $f1 ; unformatted copy to $f1 c.eq.d $f12, $f0 ; $f0 can be interpreted as double Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and provided the test case. llvm-svn: 137484
* Reverse order of operands of address operand mem so that the base operand comesAkira Hatanaka2011-07-071-7/+7
| | | | | | | before the offset. This change will enable simplification of function MipsRegisterInfo::eliminateFrameIndex. llvm-svn: 134625
* Prevent generation of redundant addiu instructions that compute address of Akira Hatanaka2011-06-241-1/+2
| | | | | | static variables or functions. llvm-svn: 133803
* Re-apply 132758 and 132768 which were speculatively reverted in 132777. Akira Hatanaka2011-06-211-0/+12
| | | | llvm-svn: 133494
* Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.Eric Christopher2011-06-091-12/+0
| | | | llvm-svn: 132777
* Initial support for inline asm memory operand constraints.Akira Hatanaka2011-06-091-0/+12
| | | | llvm-svn: 132768
* Put back removed line.Akira Hatanaka2011-06-071-0/+1
| | | | llvm-svn: 132725
* Coding style fixes.Akira Hatanaka2011-06-071-12/+0
| | | | | | | | | - Fix indentation. - Move comments. - Fit lines in 80 columns. - Remove dead code. llvm-svn: 132724
* Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.Akira Hatanaka2011-06-021-16/+17
| | | | llvm-svn: 132448
* This patch implements the thread local storage. Implemented are GeneralBruno Cardoso Lopes2011-05-311-0/+17
| | | | | | | | Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
* Define a wrapper node for target constant nodes (tglobaladdr, etc.).Akira Hatanaka2011-05-281-6/+2
| | | | | | Need this to prevent emitting illegal conditional move instructions. llvm-svn: 132240
* Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka2011-04-151-7/+7
| | | | | | in functionality. llvm-svn: 129612
* Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka2011-04-151-7/+7
| | | | | | change in functionality. llvm-svn: 129606
* Move transformation of JmpLink and related nodes done during instruction ↵Akira Hatanaka2011-04-041-56/+2
| | | | | | selection to Legalize phase. llvm-svn: 128830
* Undo changes mistakenly made in revision 128750.Akira Hatanaka2011-04-021-2/+56
| | | | llvm-svn: 128751
* Insert space before ';' to prevent warnings.Akira Hatanaka2011-04-021-56/+2
| | | | llvm-svn: 128750
* Remove redundant code. There are assignments to variables Base and Offset ↵Akira Hatanaka2011-04-011-5/+0
| | | | | | right after the code that is removed. llvm-svn: 128742
* Improve div/rem node handling on mips. Patch by Akira HatanakaBruno Cardoso Lopes2011-03-041-23/+6
| | | | llvm-svn: 127034
* Lowers block address. Currently asserts when relocation model is not PIC. ↵Bruno Cardoso Lopes2011-03-041-1/+7
| | | | | | Patch by Akira Hatanaka llvm-svn: 127027
* Remove (hopefully) all trailing whitespaces from the mips backend. Patch by ↵Bruno Cardoso Lopes2011-03-041-50/+50
| | | | | | Hatanaka, Akira llvm-svn: 127003
* Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin2010-12-231-1/+1
| | | | | | | new gcc warning that complains on self-assignments and self-initializations. llvm-svn: 122458
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-7/+7
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>Bruno Cardoso Lopes2010-11-121-0/+2
| | | | llvm-svn: 118864
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-6/+4
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* Remove Predicate_* calls from MipsJakob Stoklund Olesen2010-09-031-2/+3
| | | | llvm-svn: 112919
* Don't call Predicate_* in Mips.Jakob Stoklund Olesen2010-08-181-3/+3
| | | | llvm-svn: 111468
* SubRegIndex'ize MipsJakob Stoklund Olesen2010-05-241-6/+6
| | | | llvm-svn: 104514
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