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* [mips] Split long lines in the code. NFCSimon Atanasyan2019-11-031-8/+8
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* [mips] Mark pseudo select instructions by the `hasNoSchedulingInfo` tagSimon Atanasyan2019-06-271-2/+2
| | | | llvm-svn: 364540
* [mips] Add GPR_64 predicate to some mov[zn] instructionsSimon Atanasyan2019-06-271-8/+10
| | | | llvm-svn: 364527
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [mips] Optimize shifts for types larger than GPR size (mips2/mips3)Aleksandar Beserminji2019-01-141-0/+10
| | | | | | | | | | | | | With this patch, shifts are lowered to optimal number of instructions necessary to shift types larger than the general purpose register size. This resolves PR/32293. Thanks to Kyle Butt for reporting the issue! Differential Revision: https://reviews.llvm.org/D56320 llvm-svn: 351059
* [mips] Mark select instructions correctlySimon Dardis2018-05-151-145/+144
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46702 llvm-svn: 332364
* [mips] Move conditional moves out of isCodeGenOnlySimon Dardis2018-05-091-4/+4
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46389 llvm-svn: 331863
* [mips] Place certain 64 bit FPU instructions in their own decoder namespaceSimon Dardis2017-10-051-2/+2
| | | | | | | | | | | Previously, instructions that were defined to use the FGR64 register class were associated with the Mips64 table which was incorrect. Reviewers: nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D38454 llvm-svn: 314976
* Reland r308585Stefan Maksimovic2017-07-201-4/+4
| | | | | | | | Builder clang-x86_64-linux-abi-test apparently failed due to a spurious error unrelated to the changes r308585 introduced. llvm-svn: 308612
* Revert r308585Stefan Maksimovic2017-07-201-4/+4
| | | | | | Builder clang-x86_64-linux-abi-test seems to fail after this change llvm-svn: 308597
* [mips] Fix fp select machine verifier errorsStefan Maksimovic2017-07-201-4/+4
| | | | | | | | | | | | | | | | | Introduced FSELECT node necesary when lowering ISD::SELECT which has i32, f64, f64 as its operands. SEL_D instruction required that its output and first operand of a SELECT node, which it used, have matching types. MTC1_D64 node introduced to aid FSELECT lowering. This fixes machine verifier errors on following tests: CodeGen/Mips/llvm-ir/select-dbl.ll CodeGen/Mips/llvm-ir/select-flt.ll CodeGen/Mips/select.ll Differential Revision: https://reviews.llvm.org/D35408 llvm-svn: 308595
* Revert "[mips] Fix c.<cc>.<fmt> instruction definition."Simon Dardis2016-09-091-212/+5
| | | | | | | This reverts commit r281022. Mips buildbot broke, due to unhandled register class FCC. llvm-svn: 281033
* [mips] Fix c.<cc>.<fmt> instruction definition.Simon Dardis2016-09-091-5/+212
| | | | | | | | | | | | | | | As part of this effort, remove MipsFCmp nodes and use tablegen patterns rather than custom lowering through C++. Unexpectedly, this improves codesize for microMIPS as previous floating point setcc expansions would materialize 0 and 1 into GPRs before using the relevant mov[tf].[sd] instruction. Now $zero is used directly. Reviewers: dsanders, vkalintiris, zoran.jovanovic Differential Review: https://reviews.llvm.org/D23118 llvm-svn: 281022
* [mips] Replace AdditionalRequires<[IsGP64bit]> with GPR_64. NFC.Daniel Sanders2016-06-151-8/+4
| | | | | | | | | | | | Summary: Also fixed one case where HasMips64 was being used instead of IsGP64bit. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D21028 llvm-svn: 272771
* Revert "[mips] Promote the result of SETCC nodes to GPR width."Vasileios Kalintiris2016-03-011-152/+110
| | | | | | | | | This reverts commit r262316. It seems that my change breaks an out-of-tree chromium buildbot, so I'm reverting this in order to investigate the situation further. llvm-svn: 262387
* [mips] Promote the result of SETCC nodes to GPR width.Vasileios Kalintiris2016-03-011-110/+152
| | | | | | | | | | | | | | | | | | | | Summary: This patch modifies the existing comparison, branch, conditional-move and select patterns, and adds new ones where needed. Also, the updated SLT{u,i,iu} set of instructions generate a GPR width result. The majority of the code changes in the Mips back-end fix the wrong assumption that the result of SETCC nodes always produce an i32 value. The changes in the common code path account for the fact that in 64-bit MIPS targets, i1 is promoted to i32 instead of i64. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D10970 llvm-svn: 262316
* [mips] Add the SoftFloat MipsSubtarget feature.Toma Tabacu2015-05-071-3/+4
| | | | | | | | | | | | | | Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled. Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: jfb, llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9053 llvm-svn: 236713
* [mips] Enable code generation for MIPS-III.Vasileios Kalintiris2014-12-121-3/+9
| | | | | | | | | | | | | | | | | | Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 llvm-svn: 224128
* [mips] Support SELECT nodes for targets that don't have conditional-move ↵Vasileios Kalintiris2014-12-121-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
* [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available ↵Daniel Sanders2014-06-121-60/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
* [mips] Marked up instructions added in MIPS-IV and tested that IAS for ↵Daniel Sanders2014-05-091-16/+20
| | | | | | | | | | | | | | | | | | | | | -mcpu=mips[123] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-IV that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. Depends on D3676 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3677 llvm-svn: 208414
* [mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of ↵Daniel Sanders2014-05-071-57/+48
| | | | | | | | | | | | | | | | | FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 llvm-svn: 208213
* [mips] Continue splitting Instruction.Predicates into smaller lists and ↵Daniel Sanders2014-05-071-11/+10
| | | | | | | | | | | | | | | | | | | re-join them with !listconcat Summary: Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates No functional change (confirmed by diffing tablegen-erated files). Depends on D3639 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3640 llvm-svn: 208201
* [mips] Split Instruction.Predicates into smaller lists and re-join them with ↵Daniel Sanders2014-05-071-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | !listconcat Summary: The overall idea is to chop the Predicates list into subsets that are usually overridden independently. This allows subclasses to partially override the predicates of their superclasses without having to re-add all the existing predicates. This patch starts the process by moving HasStdEnc into a new EncodingPredicates list and almost everything else into AdditionalPredicates. It has revealed a couple likely bugs where 'let Predicates' has removed the HasStdEnc predicate. No functional change (confirmed by diffing tablegen-erated files). Depends on D3549, D3506 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3550 llvm-svn: 208184
* [mips] Move HasStdEnc to the front of the predicates lists.Daniel Sanders2014-05-071-13/+13
| | | | | | | | | | | | | | | | | | Summary: This will make it easier to prove that a more complicated change in the following commit is non-functional. No functional change. Depends on D3506 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3549 llvm-svn: 208179
* [mips] Remove two more redundant 'let Predicates = [HasStdEnc]' statements ↵Daniel Sanders2014-04-291-2/+2
| | | | | | | | | | | | | | that were missed Summary: The InstSE class already initializes Predicates to [HasStdEnc]. No functional change (confirmed by diffing tablegen-erated files before and after) Differential Revision: http://reviews.llvm.org/D3548 llvm-svn: 207558
* [mips] Fix more incorrect uses of HasMips64 and isMips64()Daniel Sanders2014-04-141-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: - Conditional moves acting on 64-bit GPR's should require MIPS-IV rather than MIPS64 - ISD::MUL, and ISD::MULH[US] should be lowered on all 64-bit ISA's Patch by David Chisnall His work was sponsored by: DARPA, AFRL I've added additional testcases to cover as much of the codegen changes affecting MIPS-IV as I can. Where I've been unable to find an existing MIPS64 testcase that can be re-used for MIPS-IV (mainly tests covering ISD::GlobalAddress and similar), I at least agree that MIPS-IV should behave like MIPS64. Further testcases that are fixed by this patch will follow in my next commit. The testcases from that commit that fail for MIPS-IV without this patch are: LLVM :: CodeGen/Mips/2010-07-20-Switch.ll LLVM :: CodeGen/Mips/cmov.ll LLVM :: CodeGen/Mips/eh-dwarf-cfa.ll LLVM :: CodeGen/Mips/largeimmprinting.ll LLVM :: CodeGen/Mips/longbranch.ll LLVM :: CodeGen/Mips/mips64-f128.ll LLVM :: CodeGen/Mips/mips64directive.ll LLVM :: CodeGen/Mips/mips64ext.ll LLVM :: CodeGen/Mips/mips64fpldst.ll LLVM :: CodeGen/Mips/mips64intldst.ll LLVM :: CodeGen/Mips/mips64load-store-left-right.ll LLVM :: CodeGen/Mips/sint-fp-store_pattern.ll Reviewers: dsanders Reviewed By: dsanders CC: matheusalmeida Differential Revision: http://reviews.llvm.org/D3343 llvm-svn: 206183
* [mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD]Daniel Sanders2014-01-211-16/+16
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
* [mips][sched] Split IIArith in preparation for the first scheduler targeting ↵Daniel Sanders2014-01-161-12/+12
| | | | | | | | | | | | | | | | | | | | | | | a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
* Support for microMIPS FPU instructions 2.Zoran Jovanovic2013-12-251-14/+14
| | | | llvm-svn: 198009
* [mips] Set instruction itineraries of loads, stores and conditional moves.Akira Hatanaka2013-09-061-15/+15
| | | | llvm-svn: 190219
* This patch adds support for microMIPS Move Conditional instructions. Test ↵Vladimir Medic2013-09-061-7/+7
| | | | | | cases are included in patch. llvm-svn: 190148
* [mips] Fix instruction definitions that were incorrectly marked as ↵Akira Hatanaka2013-08-191-6/+9
| | | | | | code-gen-only. llvm-svn: 188690
* [mips] Rename accumulator register classes and FP register operands.Akira Hatanaka2013-08-081-16/+16
| | | | llvm-svn: 188020
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-53/+53
| | | | llvm-svn: 187832
* [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates ofAkira Hatanaka2013-08-061-38/+25
| | | | | | instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
* [mips] Define instruction itineraries IIArith and IILogic.Akira Hatanaka2013-07-311-4/+4
| | | | | | No functionality change. llvm-svn: 187468
* This patch implements parsing of mips FCC register operands. The example ↵Vladimir Medic2013-07-301-11/+13
| | | | | | instructions have been added to test files. llvm-svn: 187410
* [mips] Fix FP conditional move instructions to have explicit FP condition codeAkira Hatanaka2013-07-261-8/+6
| | | | | | register operands. llvm-svn: 187242
* [mips] Fix floating point branch, comparison, and conditional move instructionsAkira Hatanaka2013-07-261-2/+2
| | | | | | | | | to have register FCC0 (the first floating point condition code register) in their Uses/Defs list. No intended functionality change. llvm-svn: 187233
* This patch represents Mips utilization of r186388 code that alows asm ↵Vladimir Medic2013-07-161-34/+36
| | | | | | matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. llvm-svn: 186397
* [mips] Fix inefficient code generation.Akira Hatanaka2013-03-011-0/+7
| | | | | | | | | | | | | This patch eliminates the need to emit a constant move instruction when this pattern is matched: (select (setgt a, Constant), T, F) The pattern above effectively turns into this: (conditional-move (setlt a, Constant + 1), F, T) llvm-svn: 176384
* Fix indentation.Akira Hatanaka2013-03-011-15/+10
| | | | llvm-svn: 176380
* [mips] Refactor conditional move instructions.Akira Hatanaka2013-01-041-13/+20
| | | | llvm-svn: 171511
* [mips] Delete all floating point instruction classes that are no longer used.Akira Hatanaka2012-12-131-31/+2
| | | | | | No functionality change. llvm-svn: 170084
* [mips] Modify definitions of floating point conditional move instructions.Akira Hatanaka2012-12-131-24/+63
| | | | | | No functionality change. llvm-svn: 170080
* [mips] Shorten predicate name.Akira Hatanaka2012-12-071-15/+15
| | | | llvm-svn: 169579
* [mips] Remove unnecessary predicates.Akira Hatanaka2012-12-071-2/+2
| | | | llvm-svn: 169577
* 1. introduce MipsPat in place of Pat in order to exclude those fromAkira Hatanaka2012-06-141-25/+33
| | | | | | | | | being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
* This patch adds a predicate to existing mips32 and mips64 so that thoseAkira Hatanaka2012-05-221-15/+17
| | | | | | | | | | | | | | | | | | | instruction encodings can be excluded during mips16 processing. This revision fixes the issue raised by Jim Grosbach. bool hasStandardEncoding() const { return !inMips16Mode(); } When micromips is added it will be bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); } No additional testing is needed other than to assure that there is no regression from this patch. Patch by Reed Kotler. llvm-svn: 157234
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