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* [mips] Split long lines in the code. NFCSimon Atanasyan2019-11-031-1/+2
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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Reland "[SelectionDAG] Enable target specific vector scalarization of calls ↵Simon Dardis2017-06-091-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and returns" By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown, backends can request that LLVM to scalarize vector types for calls and returns. The MIPS vector ABI requires that vector arguments and returns are passed in integer registers. With SelectionDAG's new hooks, the MIPS backend can now handle LLVM-IR with vector types in calls and returns. E.g. 'call @foo(<4 x i32> %4)'. Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for calls and returns if vector types were not legal. If vector types were legal, a single 128bit vector argument would be assigned to a single 32 bit / 64 bit integer register. By teaching the MIPS backend to inspect the original types, it can now implement the MIPS vector ABI which requires a particular method of scalarizing vectors. Previously, the MIPS backend relied on clang to scalarize types such as "call @foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3, i32 inreg %4)". This patch enables the MIPS backend to take either form for vector types. The previous version of this patch had a "conditional move or jump depends on uninitialized value". Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur Differential Revision: https://reviews.llvm.org/D27845 llvm-svn: 305083
* Revert "[SelectionDAG] Enable target specific vector scalarization of calls ↵Simon Dardis2017-04-071-8/+2
| | | | | | | | | | | | | and returns" This reverts commit r299766. This change appears to have broken the MIPS buildbots. Reverting while I investigate. Revert "[mips] Remove usage of debug only variable (NFC)" This reverts commit r299769. Follow up commit. llvm-svn: 299788
* [SelectionDAG] Enable target specific vector scalarization of calls and returnsSimon Dardis2017-04-071-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown, backends can request that LLVM to scalarize vector types for calls and returns. The MIPS vector ABI requires that vector arguments and returns are passed in integer registers. With SelectionDAG's new hooks, the MIPS backend can now handle LLVM-IR with vector types in calls and returns. E.g. 'call @foo(<4 x i32> %4)'. Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for calls and returns if vector types were not legal. If vector types were legal, a single 128bit vector argument would be assigned to a single 32 bit / 64 bit integer register. By teaching the MIPS backend to inspect the original types, it can now implement the MIPS vector ABI which requires a particular method of scalarizing vectors. Previously, the MIPS backend relied on clang to scalarize types such as "call @foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3, i32 inreg %4)". This patch enables the MIPS backend to take either form for vector types. Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur Differential Revision: https://reviews.llvm.org/D27845 llvm-svn: 299766
* [mips] EABI CodeGen is completely untested and seems to have bitrotted. ↵Daniel Sanders2016-06-031-48/+0
| | | | | | | | | | | | | | | | | | Remove it. Summary: There are no tests*, no EABI buildbots, and simple test cases do not work. * There is a single MIPS16 test using a mips*-gnueabi triple but this test doesn't test EABI and the triple doesn't cause EABI to be used. Reviewers: sdardis Subscribers: tberghammer, danalbert, srhines, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20906 llvm-svn: 271658
* [mips] Interrupt attribute support for mips32r2+.Vasileios Kalintiris2015-10-261-0/+25
| | | | | | | | | | | | | | | | | | | Summary: This patch adds support for using the "interrupt" attribute on Mips for interrupt handling functions. At this time only mips32r2+ with the o32 ABI with the static relocation model is supported. Unsupported configurations will be rejected Patch by Simon Dardis (+ clang-format & some trivial changes to follow the LLVM coding standards by me). Reviewers: mpf, dsanders Subscribers: dsanders, vkalintiris, llvm-commits Differential Revision: http://reviews.llvm.org/D10768 llvm-svn: 251286
* Rename the MIPS routine abiUsesSoftFloat -> useSoftFloat to matchEric Christopher2015-05-071-4/+4
| | | | | | some incoming changes and the general scheme used by features (use/has). llvm-svn: 236794
* Mips fast-isel - handle functions which return i8 or i6 .Vasileios Kalintiris2015-04-291-0/+3
| | | | | | | | | | | | | | | | Summary: Allow Mips fast-isel to handle functions which return i8/i16 signed/unsigned. Test Plan: Make check tests are forthcoming. Already passes test-suite at O0/O2 for Mips 32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6765 llvm-svn: 236103
* [MIPS] Fix justify error for small structuresPetar Jovanovic2015-03-161-1/+1
| | | | | | | | | | | | | | | Fix justify error for small structures bigger than 32 bits in fixed arguments for MIPS64 big endian. There was a problem when small structures are passed as fixed arguments. The structures that are bigger than 32 bits but smaller than 64 bits were not left justified properly on MIPS64 big endian. This is fixed by shifting the value to make it left justified when appropriate. Patch by Aleksandar Beserminji. Differential Revision: http://reviews.llvm.org/D8174 llvm-svn: 232382
* Fix justify error for small structures in varargs for MIPS64BEPetar Jovanovic2015-02-261-0/+4
| | | | | | | | | | | | | | | There was a problem when passing structures as variable arguments. The structures smaller than 64 bit were not left justified on MIPS64 big endian. This is now fixed by shifting the value to make it left- justified when appropriate. This fixes the bug http://llvm.org/bugs/show_bug.cgi?id=21608 Patch by Aleksandar Beserminji. Differential Revision: http://reviews.llvm.org/D7881 llvm-svn: 230657
* [mips] Add Mips-specific CCIf's for accessing the MipsCCState. NFC.Daniel Sanders2014-12-081-13/+28
| | | | | | | | | | | | Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6213 llvm-svn: 223662
* First stage of call lowering for Mips fast-iselReed Kotler2014-11-131-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This has most of what is needed for mips fast-isel call lowering for O32. What is missing I will add on the next patch because this patch is already too large. It should not be doing anything wrong but it will punt on some cases that it is basically capable of doing. The mechanism is there for parameters to be passed on the stack but I have not enabled it because it serves as a way for now to prevent some of the strange cases of O32 register passing that I have not fully checked yet and have some issues. The Mips O32 abi rules are very complicated as far how data is passed in floating and integer registers. However there is a way to think about this all very simply and this implementation reflects that. Basically, the ABI rules are written as if everything is passed on the stack and aligned as such. Once that is conceptually done, it is nearly trivial to reassign those locations to registers and then all the complexity disappears. So I have told tablegen that all the data is passed on the stack and during the lowering I fix this by assigning to registers as per the ABI doc. This has been my approach and you can line up what I did with the ABI document and see 1 to 1 what is going on. Test Plan: callabi.ll Reviewers: dsanders Reviewed By: dsanders Subscribers: jholewinski, echristo, ahatanak, llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D5714 llvm-svn: 221948
* [mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit ↵Daniel Sanders2014-11-071-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
* [mips] Remove MipsCC::analyzeCallOperands in favour of ↵Daniel Sanders2014-11-071-0/+7
| | | | | | | | | | | | | | | | | | CCState::AnalyzeCallOperands. NFC Summary: In addition to the usual f128 workaround, it was also necessary to provide a means of accessing ArgListEntry::IsFixed. Reviewers: theraven, vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6111 llvm-svn: 221518
* [mips] Move SpecialCallingConv to MipsCCState and use it from ↵Daniel Sanders2014-11-071-9/+13
| | | | | | | | | | | | | | | | tablegen-erated code. NFC Summary: In the long run, it should probably become a calling convention in its own right but for now just move it out of MipsISelLowering::analyzeCallOperands() so that we can drop this function in favour of CCState::AnalyzeCallOperands(). Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6085 llvm-svn: 221517
* Re-commit r221056 and others with fix, "[mips] Move F128 argument handling ↵Daniel Sanders2014-11-021-7/+33
| | | | | | | | | into MipsCCState as we did for returns. NFC." sret arguments can never originate from an f128 argument so we detect sret arguments and push false into OriginalArgWasF128. llvm-svn: 221102
* Revert r221056 and others, "[mips] Move F128 argument handling into ↵NAKAMURA Takumi2014-11-021-33/+7
| | | | | | | | | | | | | MipsCCState as we did for returns. NFC." r221056 "[mips] Move F128 argument handling into MipsCCState as we did for returns. NFC." r221058 "[mips] Fix unused variable warning introduced in r221056" r221059 "[mips] Move all ByVal handling into CCState and tablegen-erated code. NFC." r221061 "Renamed CCState members that appear to misspell 'Processed' as 'Proceed'. NFC." It cuased an undefined behavior in LLVM :: CodeGen/Mips/return-vector.ll. llvm-svn: 221081
* [mips] Move all ByVal handling into CCState and tablegen-erated code. NFC.Daniel Sanders2014-11-011-7/+18
| | | | | | | | | | | | | | | | | Summary: CCState already contains a byval implementation that is very similar to the Mips custom code. This patch merges the custom code into the existing common code and tablegen-erated code. Reviewers: vmedic Reviewed By: vmedic Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D5977 llvm-svn: 221059
* [mips] Move F128 argument handling into MipsCCState as we did for returns. NFC.Daniel Sanders2014-11-011-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: There are a couple more changes to make before analyzeFormalArguments can be merged into the standard AnalyzeFormalArguments. I've had to temporarily poke a couple holes in MipsCCState's encapsulation to save having to make all the required changes for this merge all at once*. These will be removed shortly. * We must merge our ByVal argument handling with the implementation in CCState. This will be done over the next three patches, then the fourth will merge analyzeFormalArguments with AnalyzeFormalArguments. Depends on D5967 Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5969 llvm-svn: 221056
* [tablegen] Add CustomCallingConv and use it to tablegen-erate the outermost ↵Daniel Sanders2014-11-011-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | parts of the Mips O32 implementation Summary: CustomCallingConv is simply a CallingConv that tablegen should not generate the implementation for. It allows regular CallingConv's to delegate to these custom functions. This is (currently) necessary for Mips and we cannot use CCCustom without having to adapt to the different API that CCCustom uses. This brings us a bit closer to being able to remove MipsCC::analyzeCallOperands and MipsCC::analyzeFormalArguments in favour of the common implementation. No functional change to the targets. Depends on D3341 Reviewers: vmedic Reviewed By: vmedic Subscribers: vmedic, llvm-commits Differential Revision: http://reviews.llvm.org/D5965 llvm-svn: 221052
* [mips] Fix >80-column lineDaniel Sanders2014-10-241-1/+2
| | | | llvm-svn: 220564
* [mips] Remove redundant code in RetCC_MipsN. NFC.Daniel Sanders2014-10-241-3/+0
| | | | | | | | | | | | | | | | Summary: i32 is always promoted to i64 so it no longer makes sense to assign i32 to registers. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5964 llvm-svn: 220561
* [mips] For N32/N64, structs must be passed in the upper bits of a register.Daniel Sanders2014-10-241-2/+2
| | | | | | | | | | | | | | | | | | Summary: Most structs were fixed by r218451 but those of between >32-bits and <64-bits remained broken since they were not marked with [ASZ]ExtUpper. This patch fixes the remaining cases by using CCPromoteToUpperBitsInType<i64> on i64's in addition to i32 and smaller. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5963 llvm-svn: 220556
* [mips] Return {f128} correctly for N32/N64.Daniel Sanders2014-10-071-0/+6
| | | | | | | | | | | | | | | | | Summary: According to the ABI documentation, f128 and {f128} should both be returned in $f0 and $f2. However, this doesn't match GCC's behaviour which is to return f128 in $f0 and $f2, but {f128} in $f0 and $f1. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5578 llvm-svn: 219196
* [mips] Generalize the handling of f128 return values to support f128 arguments.Daniel Sanders2014-09-261-21/+35
| | | | | | | | | | | | | | | | | | Summary: This will allow us to handle f128 arguments without duplicating code from CCState::AnalyzeFormalArguments() or CCState::AnalyzeCallOperands(). No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5292 llvm-svn: 218509
* [mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and ↵Daniel Sanders2014-09-251-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | handle struct's correctly on big-endian N32/N64 return values. Summary: The N32/N64 ABI's require that structs passed in registers are laid out such that spilling the register with 'sd' places the struct at the lowest address. For little endian this is trivial but for big-endian it requires that structs are shifted into the upper bits of the register. We also require that structs passed in registers have the 'inreg' attribute for big-endian N32/N64 to work correctly. This is because the tablegen-erated calling convention implementation only has access to the lowered form of struct arguments (one or more integers of up to 64-bits each) and is unable to determine the original type. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5286 llvm-svn: 218451
* [mips] Remove custom versions of CCState::AnalyzeReturn() and ↵Daniel Sanders2014-09-181-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CCState::AnalyzeCallReturn(). Summary: The N32/N64 ABI's return f128 values in $f0 and $f2 for hard-float and $v0 and $a0 for soft-float. The registers used in the soft-float case differ from the usual $v0, and $v1 specified for return values. Both cases were previously handled by duplicating the CCState::AnalyzeReturn() and CCState::AnalyzeCallReturn() functions and modifying them to delegate to a different assignment function for f128 and further replace the register type for the hard-float case. There is a simpler way to do both of these. We now use the common functions and select an initial assignment function based on whether the original type is f128 or not. We then handle the hard-float case using CCBitConvertToType<>. No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5269 llvm-svn: 218036
* [mips] Remove inverted predicates from MipsSubtarget that were only used by ↵Daniel Sanders2014-09-101-11/+15
| | | | | | | | | | | | | | | | MipsCallingConv.td Summary: No functional change Reviewers: echristo, vmedic Reviewed By: echristo, vmedic Subscribers: echristo, llvm-commits Differential Revision: http://reviews.llvm.org/D5266 llvm-svn: 217494
* [mips] Don't use odd-numbered float registers for double arguments for fastccSasa Stankovic2014-08-221-2/+6
| | | | | | | | calling convention if FP is 64-bit and +nooddspreg is used. Differential Revision: http://reviews.llvm.org/D4981.diff llvm-svn: 216262
* Remove the target machine from CCState. Previously it was only usedEric Christopher2014-08-061-2/+5
| | | | | | | | | to get the subtarget and that's accessible from the MachineFunction now. This helps clear the way for smaller changes where we getting a subtarget will require passing in a MachineFunction/Function as well. llvm-svn: 214988
* [mips] Don't use odd-numbered single precision registers for fastcc callingSasa Stankovic2014-07-291-2/+7
| | | | | | | | convention if -mno-odd-spreg is used. Differential Revision: http://reviews.llvm.org/D4682 llvm-svn: 214180
* [mips] Emit two CFI offset directives per double precision SDC1/LDC1Zoran Jovanovic2014-07-101-4/+5
| | | | | | | instead of just one for FR=1 registers Differential Revision: http://reviews.llvm.org/D4310 llvm-svn: 212769
* [mips] Added FPXX modeless calling convention.Zoran Jovanovic2014-07-101-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D4293 llvm-svn: 212726
* [mips] Correct callee saved list for the N32 ABI and enable testDaniel Sanders2014-04-161-2/+2
| | | | | | | | | | | | Summary: Depends on D3339 Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3340 llvm-svn: 206371
* [mips] Forbid the use of registers t6, t7 and t8 if the target is NaCl.Sasa Stankovic2014-02-071-2/+9
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D2694 llvm-svn: 200978
* Last change for mips16 prolog/epilog cleanup and optimization.Reed Kotler2013-12-151-1/+3
| | | | | | | | | Some tiny cosmetic code changes to follow. Because of the wide ranging nature of the patch a full 24 test cycle was needed to check against regression. This was the smallest patch I could make to progress from the earlier ones in the series. llvm-svn: 197350
* [mips] Add support for calling convention CC_MipsO32_FP64, which is used ↵Akira Hatanaka2013-08-201-3/+17
| | | | | | | | | | when the size of floating point registers is 64-bit. Test case will be added when support for mfhc1 and mthc1 is added. llvm-svn: 188847
* [mips] Remove predicates that were incorrectly or unnecessarily added.Akira Hatanaka2013-08-201-1/+1
| | | | llvm-svn: 188845
* Mips td file formatting: white space and long linesJack Carter2013-05-161-1/+1
| | | | llvm-svn: 182047
* Checkin in of first of several patches to finish implementation ofReed Kotler2013-05-101-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
* [mips] Remove android calling convention.Akira Hatanaka2013-03-051-12/+0
| | | | | | | This calling convention was added just to handle functions which return vector of floats. The fix committed in r165585 solves the problem. llvm-svn: 176530
* [mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 getsAkira Hatanaka2013-03-051-0/+6
| | | | | | returned in registers $2 and $4. llvm-svn: 176527
* Use the methods and classes that were added to simplify LowerCall and Akira Hatanaka2012-10-271-12/+0
| | | | | | | | LowerFormalArguments in MipsTargetLowering. No functionality change intended. llvm-svn: 166846
* Add Android ABI to Mips backend to handle functions returning vectors of fourAkira Hatanaka2012-08-161-0/+12
| | | | | | floats. llvm-svn: 162008
* Implement fastcc calling convention for MIPS.Akira Hatanaka2012-06-131-0/+52
| | | | llvm-svn: 158410
* Changes for migrating to using register mask operands.Akira Hatanaka2012-03-011-0/+17
| | | | llvm-svn: 151847
* remove blanks, and some code formatJia Liu2012-02-281-3/+3
| | | | llvm-svn: 151625
* Do not promote i32 arguments to i64. This was causing unnecessary sign extensionAkira Hatanaka2012-02-171-10/+15
| | | | | | instructions to be emitted. llvm-svn: 150782
* Remove comment.Akira Hatanaka2012-02-161-2/+0
| | | | llvm-svn: 150739
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