summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips/Mips16InstrInfo.h
Commit message (Collapse)AuthorAgeFilesLines
* Use MCRegister in copyPhysRegMatt Arsenault2019-11-111-1/+1
|
* Reland: [TII] Use optional destination and source pair as a return value; NFCDjordje Todorovic2019-11-081-4/+3
| | | | | | | | | | Refactor usage of isCopyInstrImpl, isCopyInstr and isAddImmediate methods to return optional machine operand pair of destination and source registers. Patch by Nikola Prica Differential Revision: https://reviews.llvm.org/D69622
* Revert rG57ee0435bd47f23f3939f402914c231b4f65ca5e - [TII] Use optional ↵Simon Pilgrim2019-10-311-3/+4
| | | | | | destination and source pair as a return value; NFC This is breaking MSVC builds: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/20375
* [TII] Use optional destination and source pair as a return value; NFCDjordje Todorovic2019-10-311-4/+3
| | | | | | | | | | Refactor usage of isCopyInstrImpl, isCopyInstr and isAddImmediate methods to return optional machine operand pair of destination and source registers. Patch by Nikola Prica Differential Revision: https://reviews.llvm.org/D69622
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Make TargetInstrInfo::isCopyInstr return true for regular COPY-instructionsAlexander Ivchenko2018-08-301-3/+8
| | | | | | | | | | | ..Move all target-dependent checks into new isCopyInstrImpl method. This change allows us to treat MoveReg-type instructions and generic COPY instruction in the same way Differential Revision: https://reviews.llvm.org/D49913 llvm-svn: 341072
* Change TII isCopyInstr way of returning arguments(NFC)Petar Jovanovic2018-06-061-2/+2
| | | | | | | | | | | Make TII isCopyInstr() return MachineOperands through pointer to pointer instead via reference. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D47364 llvm-svn: 334105
* [X86][MIPS][ARM] New machine instruction property 'isMoveReg'Petar Jovanovic2018-05-231-0/+3
| | | | | | | | | | | | | This property is needed in order to follow values movement between registers. This property is used in TII to implement method that returns true if simple copy like instruction is recognized, along with source and destination machine operands. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D45204 llvm-svn: 333093
* Teach TargetInstrInfo::getInlineAsmLength to parse .space directives with ↵Alex Bradbury2017-09-281-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | integer arguments It's currently quite difficult to test passes like branch relaxation, which requires branches with large displacement to be generated. The .space assembler directive makes it easy to create arbitrarily large basic blocks, but getInlineAsmLength is not able to parse it and so the size of the block is not correctly estimated. Other backends (AArch64, AMDGPU) introduce options just for testing that artificially restrict the ranges of branch instructions (e.g. aarch64-tbz-offset-bits). Although parsing a single form of the .space directive feels inelegant, it does allow a more direct testing approach. This patch adapts the .space parsing code from Mips16InstrInfo::getInlineAsmLength and removes it now the extra functionality is provided by the base implementation. I want to move this functionality to the generic getInlineAsmLength as 1) I need the same for RISC-V, and 2) I feel other backends will benefit from more direct testing of large branch displacements. Differential Revision: https://reviews.llvm.org/D37798 llvm-svn: 314393
* [Mips] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-031-8/+9
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309993
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-6/+4
| | | | | | | | This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. llvm-svn: 272512
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* [mips] Expose adjustStackPtr() from MipsInstrInfo. NFC.Vasileios Kalintiris2015-04-021-1/+1
| | | | | | | | | | | | | | | | | Summary: adjustStackPtr() is implemented from both MipsSEInstrInfo and Mips16InstrInfo. It makes sense to expose this function from MipsInstrInfo and avoid explicit casting in some cases. Depends on D8638. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8640 llvm-svn: 233905
* Remove the need to cache the subtarget in the Mips TargetRegisterInfoEric Christopher2015-03-121-1/+1
| | | | | | classes. llvm-svn: 232012
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Make InstrInfo depend only upon the Subtarget getting passed inEric Christopher2014-07-181-1/+1
| | | | | | rather than the TargetMachine. llvm-svn: 213425
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-25/+25
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition llvm-svn: 207506
* Delete dead code.Reed Kotler2013-12-061-5/+0
| | | | llvm-svn: 196551
* Allow the code which returns the length for inline assembler to knowReed Kotler2013-11-131-0/+2
| | | | | | | | | specifically about the .space directive. This allows us to force large blocks of code to appear in test cases for things like constant islands without having to make giant test cases to force things like long branches to take effect. llvm-svn: 194555
* Clean up code for Mips16 large frame handling.Reed Kotler2013-08-041-1/+8
| | | | llvm-svn: 187701
* [mips] Rename functions. No functionality changes.Akira Hatanaka2013-05-131-2/+2
| | | | llvm-svn: 181713
* [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.Akira Hatanaka2013-03-291-11/+13
| | | | | | No functionality changes. llvm-svn: 178327
* Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.Reed Kotler2013-02-251-14/+0
| | | | llvm-svn: 176007
* Make psuedo FEXT_T8I816_ins into a custom emitter.Reed Kotler2013-02-241-8/+0
| | | | llvm-svn: 176002
* Expand pseudos/macros:Reed Kotler2013-02-201-0/+14
| | | | | | | | SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16 $T8 shows up as register $24 when emitted from C++ code so we had to change some tests that were already there for this functionality. llvm-svn: 175593
* Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.Reed Kotler2013-02-191-0/+5
| | | | llvm-svn: 175474
* Beginning of expanding all current mips16 macro/pseudo instruction sequences.Reed Kotler2013-02-181-1/+3
| | | | | | | | | | This expansion will be moved to expandISelPseudos as soon as I can figure out how to do that. There are other instructions which use this ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all, I will delete the macro asm string text so it has no way to be used in the future. llvm-svn: 175413
* One more try to make this look nice. I have lots of pseudo lowering Reed Kotler2013-02-161-0/+3
| | | | | | | | as well as 16/32 bit variants to do and so I want this to look nice when I do it. I've been experimenting with this. No new test cases are needed. llvm-svn: 175369
* Use a different scheme to chose 16/32 variants. This scheme is moreReed Kotler2013-02-161-3/+1
| | | | | | | consistent with how BuildMI works. No new tests needed. All should work the same as before. llvm-svn: 175342
* For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler2013-02-131-0/+12
| | | | | | | | | | if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. llvm-svn: 175073
* When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler2013-02-081-5/+7
| | | | | | | | allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. llvm-svn: 174696
* [mips] 80 columns.Akira Hatanaka2013-01-041-2/+3
| | | | llvm-svn: 171515
* fix most of remaining issues with large frames.Reed Kotler2012-12-201-0/+27
| | | | | | | | | | these patches are tested a lot by test-suite but make check tests are forthcoming once the next few patches that complete this are committed. with the next few patches the pass rate for mips16 is near 100% llvm-svn: 170656
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-041-1/+1
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] llvm-svn: 169224
* Implement ADJCALLSTACKUP and ADJCALLSTACKDOWNReed Kotler2012-10-311-0/+4
| | | | llvm-svn: 167107
* Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo andAkira Hatanaka2012-07-311-0/+5
| | | | | | MipsSERegisterInfo. llvm-svn: 161092
* Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),Akira Hatanaka2012-07-311-0/+71
and MipsSEInstrInfo (for mips32/64). llvm-svn: 161081
OpenPOWER on IntegriCloud