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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [MIPS GlobalISel] Add pre legalizer combiner passPetar Avramovic2019-01-141-0/+2
| | | | | | | | | | Introduce GlobalISel pre legalizer pass for MIPS. It will be used to cope with instructions that require combining before legalization. Differential Revision: https://reviews.llvm.org/D56269 llvm-svn: 351046
* [mips] Fix atomic operations at O0, v3Aleksandar Beserminji2018-07-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Similar to PR/25526, fast-regalloc introduces spills at the end of basic blocks. When this occurs in between an ll and sc, the stores can cause the atomic sequence to fail. This patch fixes the issue by introducing more pseudos to represent atomic operations and moving their lowering to after the expansion of postRA pseudos. This version addresses issues with the initial implementation and covers all atomic operations. This resolves PR/32020. Thanks to James Cowgill for reporting the issue! Patch By: Simon Dardis Differential Revision: https://reviews.llvm.org/D31287 llvm-svn: 336328
* [mips][microMIPS] Extending size reduction pass with LWP and SWPZoran Jovanovic2018-06-131-1/+3
| | | | | | | | | | | | Author: milena.vujosevic.janicic Reviewers: sdardis The patch extends size reduction pass for MicroMIPS. It introduces reduction of two instructions into one instruction: Two SW instructions are transformed into one SWP instrucition. Two LW instructions are transformed into one LWP instrucition. Differential Revision: https://reviews.llvm.org/D39115 llvm-svn: 334595
* [mips] Merge MipsLongBranch and MipsHazardSchedule passesAleksandar Beserminji2018-05-221-3/+2
| | | | | | | | | | | | | | MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it potentially breaks some jumps, so they have to be expanded to long branches. When some branch is expanded to long branch, it potentially creates a hazard situation, which should be fixed by adding nops. New pass is called MipsBranchExpansion, it combines these two passes, and runs them alternately until one of them reports no changes were made. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332977
* [mips] Revert Merge MipsLongBranch and MipsHazardSchedule passesAleksandar Beserminji2018-05-211-2/+3
| | | | | | | | Revert this patch due buildbot failure. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332837
* [mips] Merge MipsLongBranch and MipsHazardSchedule passesAleksandar Beserminji2018-05-211-3/+2
| | | | | | | | | | | | | | MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it potentially breaks some jumps, so they have to be expanded to long branches. When some branch is expanded to long branch, it potentially creates a hazard situation, which should be fixed by adding nops. New pass is called MipsBranchExpansion, it combines these two passes, and runs them alternately until one of them reports no changes were made. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332834
* [mips] Initialize the long branch pass for testing purposesSimon Dardis2018-05-121-0/+1
| | | | llvm-svn: 332172
* [mips] Rename Filler to MipsDelaySlotFiller and initialize the passSimon Dardis2018-05-111-0/+2
| | | | llvm-svn: 332102
* [MIPS GlobalISel] Adding GlobalISelPetar Jovanovic2018-02-231-0/+8
| | | | | | | | | | | Add GlobalISel infrastructure up to the point where we can select a ret void. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D43583 llvm-svn: 325888
* [LegacyPassManager] Remove TargetMachine constructorsFrancis Visoiu Mistrih2017-05-181-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides a new way to access the TargetMachine through TargetPassConfig, as a dependency. The patterns replaced here are: * Passes handling a null TargetMachine call `getAnalysisIfAvailable<TargetPassConfig>`. * Passes not handling a null TargetMachine `addRequired<TargetPassConfig>` and call `getAnalysis<TargetPassConfig>`. * MachineFunctionPasses now use MF.getTarget(). * Remove all the TargetMachine constructors. * Remove INITIALIZE_TM_PASS. This fixes a crash when running `llc -start-before prologepilog`. PEI needs StackProtector, which gets constructed without a TargetMachine by the pass manager. The StackProtector pass doesn't handle the case where there is no TargetMachine, so it segfaults. Related to PR30324. Differential Revision: https://reviews.llvm.org/D33222 llvm-svn: 303360
* [mips][microMIPS] Adding code size reduction pass for MicroMIPSZoran Jovanovic2017-04-271-0/+1
| | | | | | | | | | | | | | | Author: milena.vujosevic.janicic Reviewers: sdardis The code implements size reduction pass for MicroMIPS. Load and store instructions are examined and transformed, if possible. lw32 instruction is transformed into 16-bit instruction lwsp sw32 instruction is transformed into 16-bit instruction swsp Arithmetic instrcutions are examined and transformed, if possible. addu32 instruction is transformed into 16-bit instruction addu16 subu32 instruction is transformed into 16-bit instruction subu16 Differential Revision: https://reviews.llvm.org/D15144 llvm-svn: 301540
* [mips] Revert fixes for PR32020.Simon Dardis2017-03-091-1/+0
| | | | | | | | | | | | | | | The fix introduces segfaults and clobbers the value to be stored when the atomic sequence loops. Revert "[Target/MIPS] Kill dead code, no functional change intended." This reverts commit r296153. Revert "Recommit "[mips] Fix atomic compare and swap at O0."" This reverts commit r296134. llvm-svn: 297380
* Recommit "[mips] Fix atomic compare and swap at O0."Simon Dardis2017-02-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | This time with the missing files. Similar to PR/25526, fast-regalloc introduces spills at the end of basic blocks. When this occurs in between an ll and sc, the store can cause the atomic sequence to fail. This patch fixes the issue by introducing more pseudos to represent atomic operations and moving their lowering to after the expansion of postRA pseudos. This resolves PR/32020. Thanks to James Cowgill for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D30257 llvm-svn: 296134
* Revert "[mips] Fix atomic compare and swap at O0."Simon Dardis2017-02-241-1/+0
| | | | | | This reverts r296132. I forgot to include the tests. llvm-svn: 296133
* [mips] Fix atomic compare and swap at O0.Simon Dardis2017-02-241-0/+1
| | | | | | | | | | | | | | | | | | | | Similar to PR/25526, fast-regalloc introduces spills at the end of basic blocks. When this occurs in between an ll and sc, the store can cause the atomic sequence to fail. This patch fixes the issue by introducing more pseudos to represent atomic operations and moving their lowering to after the expansion of postRA pseudos. This resolves PR/32020. Thanks to James Cowgill for reporting the issue! Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D30257 llvm-svn: 296132
* Delete dead code. NFC.Rafael Espindola2016-06-281-1/+1
| | | | llvm-svn: 274020
* [Mips] Fix -Wunused-private-field warning after r263444.Chad Rosier2016-03-141-1/+1
| | | | llvm-svn: 263454
* [mips] MIPS32R6 compact branch supportDaniel Sanders2016-03-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: MIPSR6 introduces a class of branches called compact branches. Unlike the traditional MIPS branches which have a delay slot, compact branches do not have a delay slot. The instruction following the compact branch is only executed if the branch is not taken and must not be a branch. It works by generating compact branches for MIPS32R6 when the delay slot filler cannot fill a delay slot. Then, inspecting the generated code for forbidden slot hazards (a compact branch with an adjacent branch or other CTI) and inserting nops to clear this hazard. Patch by Simon Dardis. Reviewers: vkalintiris, dsanders Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16353 llvm-svn: 263444
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* [mips] Remove trivial header for the MipsModuleISelDAGToDAG pass. NFC.Vasileios Kalintiris2015-03-141-0/+1
| | | | llvm-svn: 232260
* [mips] Remove trivial header for the Mips16HardFloat pass. NFC.Vasileios Kalintiris2015-03-141-0/+1
| | | | llvm-svn: 232259
* [mips] Remove trivial header for the MipsOs16 pass. NFC.Vasileios Kalintiris2015-03-141-0/+3
| | | | llvm-svn: 232258
* Remove most of the TargetMachine::getSubtarget/getSubtargetImplEric Christopher2015-01-291-1/+0
| | | | | | | | | calls that don't take a Function argument from Mips. Notable exceptions: the AsmPrinter and MipsTargetObjectFile. The latter needs to be fixed, and the former will be fixed when the general AsmPrinter changes happen. llvm-svn: 227512
* Reinstate "Nuke the old JIT."Eric Christopher2014-09-021-2/+0
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-071-0/+2
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Nuke the old JIT.Rafael Espindola2014-08-071-2/+0
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* [mips] Revert test commit r195922.Daniel Sanders2013-11-281-1/+0
| | | | llvm-svn: 195923
* [mips] A test commit to test my Herald and Audit workflowDaniel Sanders2013-11-281-0/+1
| | | | | | Will be reverted in the next commit llvm-svn: 195922
* [mips] Implement the following optimizations using dominance information toAkira Hatanaka2013-11-271-0/+1
| | | | | | | | | | | make PIC calls a little more efficient: 1. Remove instructions setting up $gp if it is known that a function has been called at least once. 2. Save the address of a called function in a register instead of loading it from the GOT at every call site. llvm-svn: 195892
* Turn MipsOptimizeMathLibCalls into a target-independent scalar transformRichard Sandiford2013-08-231-1/+0
| | | | | | | | | | ...so that it can be used for z too. Most of the code is the same. The only real change is to use TargetTransformInfo to test when a sqrt instruction is available. The pass is opt-in because at the moment it only handles sqrt. llvm-svn: 189097
* [mips] Add an IR transformation pass that optimizes calls to sqrt.Akira Hatanaka2013-06-111-1/+1
| | | | | | | | | The pass emits a call to sqrt that has attribute "read-none". This call will be converted to an ISD::FSQRT node during DAG construction, which will turn into a mips native sqrt instruction. llvm-svn: 183802
* Add the skeleton for the Mips constant island pass.Reed Kotler2013-02-271-0/+1
| | | | | | | It will only be used for Mips 16 at this time. llvm-svn: 176161
* Add long branch expansion pass for MIPS.Akira Hatanaka2012-06-141-0/+1
| | | | llvm-svn: 158433
* Move the code in MipsExpandPseudo to MipsInstrInfo::expandPostRAPseudo.Akira Hatanaka2012-05-251-2/+0
| | | | | | Delete MipsExpandPseudo. llvm-svn: 157495
* Remove MipsEmitGPRestore.cpp.Akira Hatanaka2012-05-121-1/+0
| | | | llvm-svn: 156696
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-2/+0
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Added the infrastructute necessary for MIPS JIT support. Patch by VladimirBruno Cardoso Lopes2011-07-211-0/+3
| | | | | | | | Stefanovic. I removed the part that actually emits the instructions cause I want that to get in better shape first and in incremental steps. This also makes it easier to review the upcoming parts. llvm-svn: 135678
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-12/+1
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-1/+2
| | | | llvm-svn: 134024
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-271-1/+2
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Prevent instructions using $gp from being placed between a jalr and the ↵Akira Hatanaka2011-05-041-0/+1
| | | | | | instruction that restores the clobbered $gp. llvm-svn: 130847
* Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka2011-04-151-3/+3
| | | | | | in functionality. llvm-svn: 129612
* Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka2011-04-151-3/+3
| | | | | | change in functionality. llvm-svn: 129606
* Add pass that expands pseudo instructions into target instructions after ↵Akira Hatanaka2011-04-151-0/+1
| | | | | | register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. llvm-svn: 129594
* Remove (hopefully) all trailing whitespaces from the mips backend. Patch by ↵Bruno Cardoso Lopes2011-03-041-1/+1
| | | | | | Hatanaka, Akira llvm-svn: 127003
* Add new helpers for registering targets.Daniel Dunbar2009-07-251-3/+0
| | | | | | - Less boilerplate == good. llvm-svn: 77052
* Put Target definitions inside Target specific header, and llvm namespace.Daniel Dunbar2009-07-181-0/+4
| | | | llvm-svn: 76344
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